High-performance systolic arrays for band matrix multiplication

Yun Yang, Wenqing Zhao, Yasuaki Inoue

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    8 Citations (Scopus)

    Abstract

    Band matrix multiplication is widely used in DSP systems. However traditional Kung-Leiserson systolic array for band matrix multiplication cannot be realized with high cell-efficiency. In this paper, three high-performance band matrix multiplication systolic arrays (BMMSA) are presented based on the ideas of "Matrix Compression" and "Super Pipelined". These new systolic arrays are realized by compressing the data matrix skillfully and adjusting the operation sequence carefully. The results show that the best systolic array for band matrix multiplication uses almost 100% processing elements(PE) in each step. Also, these modifications increase the operation speed and at best spend only 1/3 processing time to complete the multiplication operation.

    Original languageEnglish
    Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
    Pages1130-1133
    Number of pages4
    DOIs
    Publication statusPublished - 2005
    EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
    Duration: 2005 May 232005 May 26

    Other

    OtherIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005
    CountryJapan
    CityKobe
    Period05/5/2305/5/26

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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  • Cite this

    Yang, Y., Zhao, W., & Inoue, Y. (2005). High-performance systolic arrays for band matrix multiplication. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 1130-1133). [1464792] https://doi.org/10.1109/ISCAS.2005.1464792