High performance VLSI architecture of fractional motion estimation in H.264 for HDTV

J. Changqi Yang, Satoshi Goto, Takeshi Ikenaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

49 Citations (Scopus)

Abstract

Fractional Motion Estimation (FME) on sub-pixels will occupy almost over 45% of the computation complexity of H.264 encoding process. Therefore a high performance VLSI architecture of FME is described in this paper to achieve the capacity of encoding the high-resolution real-time video stream for HDTV. Our design is improved from an existing work by involving a pipeline strategy in sub-pixel interpolation unit which can avoid the long delay paths in 6-tap ID FIR so as to increase the clock frequency up to 200MHz. Moreover, a 16-pixel search engine is adopted to remove the redundant interpolation area and parallelize the various block size search which can save more than half of the clock cycles in processing a macro block. Our design is implemented with only 189K gates at operating frequency of 200MHz in worst case(285MHz in typical case). It can provide the processing capacity of more than 250K MB/sec which is enough for 1080HD (1920×1088) video streams at frame rate of 30fps. It is a useful Intellectual Property (IP) design for multimedia system.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Pages2605-2608
Number of pages4
Publication statusPublished - 2006
EventISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos
Duration: 2006 May 212006 May 24

Other

OtherISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
CityKos
Period06/5/2106/5/24

Fingerprint

High definition television
Motion estimation
Pixels
Clocks
Interpolation
Multimedia systems
Intellectual property
Search engines
Processing
Macros
Pipelines

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Yang, J. C., Goto, S., & Ikenaga, T. (2006). High performance VLSI architecture of fractional motion estimation in H.264 for HDTV. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 2605-2608). [1693157]

High performance VLSI architecture of fractional motion estimation in H.264 for HDTV. / Yang, J. Changqi; Goto, Satoshi; Ikenaga, Takeshi.

Proceedings - IEEE International Symposium on Circuits and Systems. 2006. p. 2605-2608 1693157.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yang, JC, Goto, S & Ikenaga, T 2006, High performance VLSI architecture of fractional motion estimation in H.264 for HDTV. in Proceedings - IEEE International Symposium on Circuits and Systems., 1693157, pp. 2605-2608, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, 06/5/21.
Yang JC, Goto S, Ikenaga T. High performance VLSI architecture of fractional motion estimation in H.264 for HDTV. In Proceedings - IEEE International Symposium on Circuits and Systems. 2006. p. 2605-2608. 1693157
Yang, J. Changqi ; Goto, Satoshi ; Ikenaga, Takeshi. / High performance VLSI architecture of fractional motion estimation in H.264 for HDTV. Proceedings - IEEE International Symposium on Circuits and Systems. 2006. pp. 2605-2608
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