High speed and throughput evaluation of SHA-1 hash function design with pipelining and unfolding transformation techniques

Shamsiah Binti Suhaili, Takahiro Watanabe, Norhuzaimin Julai

Research output: Contribution to journalArticle


In recent years, designing of SHA-1 hash function has become popular because it was important in security design application. One of the applications of SHA-1 hash function was HMAC where the architecture of SHA-1 needed to be improved in terms of speed and throughput in order to obtain the high-performance design. The objective of this project was to design high speed and throughput evaluation of SHA-1 hash function based on a combination of pipelining and unfolding techniques. By using both techniques in designing the architecture of SHA-1 design, the speed of SHA-1 hash function can be increased significantly as well as throughput of the design. In this paper, five proposed SHA-1 architectures were designed with different stages of pipelining such as 1, 4 and 40 stages. The results showed the high-speed design of SHA-1 design can be obtained by using 40 stages pipelining with unfolding factor two. This design provided a high-speed implementation with maximum frequency of 308.17 MHz on Arria II GX and 458.59 MHz on Virtex 5 XC5VLX50T. Furthermore, the throughput of the design also increased about 150.269 Gbps and 223.618 Gbps on Arria II GX and Virtex 5 XC5VLX50T respectively. Thus, high-speed design of SHA-1 hash function was successfully obtained which can give benefit to society especially in security system data transmission and other types of hash functions.

Original languageEnglish
Pages (from-to)19-22
Number of pages4
JournalJournal of Telecommunication, Electronic and Computer Engineering
Issue number3-10
Publication statusPublished - 2017 Jan 1



  • FPGA
  • Pipelining
  • SHA-1 hash function
  • Unfolding transformation

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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