High speed page mode sensing scheme for EPROM's and flash EEPROM's using divided bit line architecture

Yasushi Terada; Takeshi Nakayama; Kazuo Kobayashi; Masanori Hayashikoshi; Shin ichi Kobayashi; Yoshikazu Miyawaki; Natsuo Ajika; Hideaki Arima; Tsutomu Yoshihara

High speed page mode sensing scheme for EPROM's and flash EEPROM's using divided bit line architecture

Yasushi Terada^*, Takeshi Nakayama, Kazuo Kobayashi, Masanori Hayashikoshi, Shin ichi Kobayashi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

A novel high-speed page mode sense scheme for EPROMs and flash EEPROMs has been developed. A divided bit line architecture makes it possible to adopt a folded bit line architecture in which sense amplifiers are located at the end of the bit lines. Dynamic sensing avoids the soft write problem by reducing bit line voltage and the current flow through the memory cell. An experimental 1-Mb flash EEPROM using a 0.6-μm design rule has been designed. Simulated results show that a high-speed address access time of 60 ns and a page mode access time of 15 ns can be achieved.

Original language	English
Title of host publication	90 Symp VLSI Circuits
Place of Publication	Piscataway, NJ, United States
Publisher	Publ by IEEE
Pages	97-98
Number of pages	2
Publication status	Published - 1990
Externally published	Yes
Event	1990 Symposium on VLSI Circuits - Honolulu, HI, USA Duration: 1990 Jun 7 → 1990 Jun 9

Other

Other	1990 Symposium on VLSI Circuits
City	Honolulu, HI, USA
Period	90/6/7 → 90/6/9

ASJC Scopus subject areas

Engineering(all)

Cite this

@inproceedings{6df1090faa82450f8740e4f261f77e4e,

title = "High speed page mode sensing scheme for EPROM's and flash EEPROM's using divided bit line architecture",

abstract = "A novel high-speed page mode sense scheme for EPROMs and flash EEPROMs has been developed. A divided bit line architecture makes it possible to adopt a folded bit line architecture in which sense amplifiers are located at the end of the bit lines. Dynamic sensing avoids the soft write problem by reducing bit line voltage and the current flow through the memory cell. An experimental 1-Mb flash EEPROM using a 0.6-μm design rule has been designed. Simulated results show that a high-speed address access time of 60 ns and a page mode access time of 15 ns can be achieved.",

author = "Yasushi Terada and Takeshi Nakayama and Kazuo Kobayashi and Masanori Hayashikoshi and Kobayashi, {Shin ichi} and Yoshikazu Miyawaki and Natsuo Ajika and Hideaki Arima and Tsutomu Yoshihara",

year = "1990",

language = "English",

pages = "97--98",

booktitle = "90 Symp VLSI Circuits",

publisher = "Publ by IEEE",

note = "1990 Symposium on VLSI Circuits ; Conference date: 07-06-1990 Through 09-06-1990",

}

TY - GEN

T1 - High speed page mode sensing scheme for EPROM's and flash EEPROM's using divided bit line architecture

AU - Terada, Yasushi

AU - Nakayama, Takeshi

AU - Kobayashi, Kazuo

AU - Hayashikoshi, Masanori

AU - Kobayashi, Shin ichi

AU - Miyawaki, Yoshikazu

AU - Ajika, Natsuo

AU - Arima, Hideaki

AU - Yoshihara, Tsutomu

PY - 1990

Y1 - 1990

N2 - A novel high-speed page mode sense scheme for EPROMs and flash EEPROMs has been developed. A divided bit line architecture makes it possible to adopt a folded bit line architecture in which sense amplifiers are located at the end of the bit lines. Dynamic sensing avoids the soft write problem by reducing bit line voltage and the current flow through the memory cell. An experimental 1-Mb flash EEPROM using a 0.6-μm design rule has been designed. Simulated results show that a high-speed address access time of 60 ns and a page mode access time of 15 ns can be achieved.

AB - A novel high-speed page mode sense scheme for EPROMs and flash EEPROMs has been developed. A divided bit line architecture makes it possible to adopt a folded bit line architecture in which sense amplifiers are located at the end of the bit lines. Dynamic sensing avoids the soft write problem by reducing bit line voltage and the current flow through the memory cell. An experimental 1-Mb flash EEPROM using a 0.6-μm design rule has been designed. Simulated results show that a high-speed address access time of 60 ns and a page mode access time of 15 ns can be achieved.

UR - http://www.scopus.com/inward/record.url?scp=0025559292&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0025559292&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0025559292

SP - 97

EP - 98

BT - 90 Symp VLSI Circuits

PB - Publ by IEEE

CY - Piscataway, NJ, United States

T2 - 1990 Symposium on VLSI Circuits

Y2 - 7 June 1990 through 9 June 1990

ER -

High speed page mode sensing scheme for EPROM's and flash EEPROM's using divided bit line architecture

Abstract

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ASJC Scopus subject areas

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