High speed page mode sensing scheme for EPROM's and flash EEPROM's using divided bit line architecture

Yasushi Terada, Takeshi Nakayama, Kazuo Kobayashi, Masanori Hayashikoshi, Shin ichi Kobayashi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Tsutomu Yoshihara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A novel high-speed page mode sense scheme for EPROMs and flash EEPROMs has been developed. A divided bit line architecture makes it possible to adopt a folded bit line architecture in which sense amplifiers are located at the end of the bit lines. Dynamic sensing avoids the soft write problem by reducing bit line voltage and the current flow through the memory cell. An experimental 1-Mb flash EEPROM using a 0.6-μm design rule has been designed. Simulated results show that a high-speed address access time of 60 ns and a page mode access time of 15 ns can be achieved.

Original languageEnglish
Title of host publication90 Symp VLSI Circuits
Place of PublicationPiscataway, NJ, United States
PublisherPubl by IEEE
Pages97-98
Number of pages2
Publication statusPublished - 1990
Externally publishedYes
Event1990 Symposium on VLSI Circuits - Honolulu, HI, USA
Duration: 1990 Jun 71990 Jun 9

Other

Other1990 Symposium on VLSI Circuits
CityHonolulu, HI, USA
Period90/6/790/6/9

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Terada, Y., Nakayama, T., Kobayashi, K., Hayashikoshi, M., Kobayashi, S. I., Miyawaki, Y., Ajika, N., Arima, H., & Yoshihara, T. (1990). High speed page mode sensing scheme for EPROM's and flash EEPROM's using divided bit line architecture. In 90 Symp VLSI Circuits (pp. 97-98). Publ by IEEE.