High speed page mode sensing scheme for EPROM's and flash EEPROM's using divided bit line architecture

Yasushi Terada*, Takeshi Nakayama, Kazuo Kobayashi, Masanori Hayashikoshi, Shin ichi Kobayashi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Tsutomu Yoshihara

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

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Engineering & Materials Science