High-speed parallel sensing architecture for multi-megabit flash E2PROM's

Kazuo Kobayashi, Takeshi Nakayama, Yoshikazu Miyawaki, Masanori Hayashikoshi, Yasushi Terada, Tsutomu Yoshihara

Research output: Contribution to journalArticle

5 Citations (Scopus)


A high-speed parallel sensing architecture for high-density 5-V-only flash E2PROMs is described. A source-biasing technique enhances the cell current while minimizing the read disturbance problem. Flip-flop-type differential sense amplifiers are arranged between every two pairs of bit lines, so that half the memory cells on the same work line are sensed simultaneously. Self-time dynamic sensing was developed for high speed and stable sensing and also decreased read disturbance and operating current. Simulated results show that a sub-10-μA cell current is successfully sensed in 40 ns. In the program mode, the differential amplifier acts as a column latch, which substantially reduces the chip size.

Original languageEnglish
Pages (from-to)79-83
Number of pages5
JournalIEEE Journal of Solid-State Circuits
Issue number1
Publication statusPublished - 1990 Feb
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'High-speed parallel sensing architecture for multi-megabit flash E<sup>2</sup>PROM's'. Together they form a unique fingerprint.

  • Cite this

    Kobayashi, K., Nakayama, T., Miyawaki, Y., Hayashikoshi, M., Terada, Y., & Yoshihara, T. (1990). High-speed parallel sensing architecture for multi-megabit flash E2PROM's. IEEE Journal of Solid-State Circuits, 25(1), 79-83. https://doi.org/10.1109/4.50288