High-throughput decoder for low-density parity-check code

Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

We have designed and implemented the LDPC decoder chip with memory-reduction method to achieve high-throughput and practical chip size. The decoder decodes (3,6)-2304bit regular LDPC codes using modified min-sum algorithm. The decoder achieves a throughput of 530Mb/s at an operating frequency of 147MHz. The chip has been fabricated in a 0.18μm, 6 metal-layer CMOS technology. The chip size is 36mm2.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages112-113
Number of pages2
Volume2006
Publication statusPublished - 2006
EventASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 - Yokohama
Duration: 2006 Jan 242006 Jan 27

Other

OtherASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
CityYokohama
Period06/1/2406/1/27

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Throughput
Data storage equipment
Metals

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Ishikawa, T., Shimizu, K., Ikenaga, T., & Goto, S. (2006). High-throughput decoder for low-density parity-check code. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (Vol. 2006, pp. 112-113). [1594662]

High-throughput decoder for low-density parity-check code. / Ishikawa, Tatsuyuki; Shimizu, Kazunori; Ikenaga, Takeshi; Goto, Satoshi.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2006 2006. p. 112-113 1594662.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ishikawa, T, Shimizu, K, Ikenaga, T & Goto, S 2006, High-throughput decoder for low-density parity-check code. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. vol. 2006, 1594662, pp. 112-113, ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006, Yokohama, 06/1/24.
Ishikawa T, Shimizu K, Ikenaga T, Goto S. High-throughput decoder for low-density parity-check code. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2006. 2006. p. 112-113. 1594662
Ishikawa, Tatsuyuki ; Shimizu, Kazunori ; Ikenaga, Takeshi ; Goto, Satoshi. / High-throughput decoder for low-density parity-check code. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2006 2006. pp. 112-113
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