High-throughput LDPC decoder for long code-length

Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

We have designed and implemented the LDPC decoder with memory-reduction method to achieve high-throughput and practical hardware size for long code-length. The decoder decodes (3,6)-11520-rbit regular LDPC codes using modified minsum algorithm. The decoder achieves a throughput of 312 Mb/s at an operating frequency of 69 MHz with 20 iterative decoding. The gate count is 2M gates.

Original languageEnglish
Title of host publication2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers
Pages101-104
Number of pages4
DOIs
Publication statusPublished - 2007
Event2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Hsinchu
Duration: 2007 Apr 262007 Apr 28

Other

Other2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006
CityHsinchu
Period07/4/2607/4/28

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Throughput
Iterative decoding
Hardware
Data storage equipment

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Ishikawa, T., Shimizu, K., Ikenaga, T., & Goto, S. (2007). High-throughput LDPC decoder for long code-length. In 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers (pp. 101-104). [4027506] https://doi.org/10.1109/VDAT.2006.258134

High-throughput LDPC decoder for long code-length. / Ishikawa, Tatsuyuki; Shimizu, Kazunori; Ikenaga, Takeshi; Goto, Satoshi.

2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. p. 101-104 4027506.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ishikawa, T, Shimizu, K, Ikenaga, T & Goto, S 2007, High-throughput LDPC decoder for long code-length. in 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers., 4027506, pp. 101-104, 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006, Hsinchu, 07/4/26. https://doi.org/10.1109/VDAT.2006.258134
Ishikawa T, Shimizu K, Ikenaga T, Goto S. High-throughput LDPC decoder for long code-length. In 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. p. 101-104. 4027506 https://doi.org/10.1109/VDAT.2006.258134
Ishikawa, Tatsuyuki ; Shimizu, Kazunori ; Ikenaga, Takeshi ; Goto, Satoshi. / High-throughput LDPC decoder for long code-length. 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. pp. 101-104
@inproceedings{63bfbca9906b4a4b981580b38dfb4330,
title = "High-throughput LDPC decoder for long code-length",
abstract = "We have designed and implemented the LDPC decoder with memory-reduction method to achieve high-throughput and practical hardware size for long code-length. The decoder decodes (3,6)-11520-rbit regular LDPC codes using modified minsum algorithm. The decoder achieves a throughput of 312 Mb/s at an operating frequency of 69 MHz with 20 iterative decoding. The gate count is 2M gates.",
author = "Tatsuyuki Ishikawa and Kazunori Shimizu and Takeshi Ikenaga and Satoshi Goto",
year = "2007",
doi = "10.1109/VDAT.2006.258134",
language = "English",
isbn = "1424401798",
pages = "101--104",
booktitle = "2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers",

}

TY - GEN

T1 - High-throughput LDPC decoder for long code-length

AU - Ishikawa, Tatsuyuki

AU - Shimizu, Kazunori

AU - Ikenaga, Takeshi

AU - Goto, Satoshi

PY - 2007

Y1 - 2007

N2 - We have designed and implemented the LDPC decoder with memory-reduction method to achieve high-throughput and practical hardware size for long code-length. The decoder decodes (3,6)-11520-rbit regular LDPC codes using modified minsum algorithm. The decoder achieves a throughput of 312 Mb/s at an operating frequency of 69 MHz with 20 iterative decoding. The gate count is 2M gates.

AB - We have designed and implemented the LDPC decoder with memory-reduction method to achieve high-throughput and practical hardware size for long code-length. The decoder decodes (3,6)-11520-rbit regular LDPC codes using modified minsum algorithm. The decoder achieves a throughput of 312 Mb/s at an operating frequency of 69 MHz with 20 iterative decoding. The gate count is 2M gates.

UR - http://www.scopus.com/inward/record.url?scp=34748907834&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34748907834&partnerID=8YFLogxK

U2 - 10.1109/VDAT.2006.258134

DO - 10.1109/VDAT.2006.258134

M3 - Conference contribution

SN - 1424401798

SN - 9781424401796

SP - 101

EP - 104

BT - 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

ER -