Abstract
We have designed and implemented the LDPC decoder with memory-reduction method to achieve high-throughput and practical hardware size for long code-length. The decoder decodes (3,6)-11520-rbit regular LDPC codes using modified minsum algorithm. The decoder achieves a throughput of 312 Mb/s at an operating frequency of 69 MHz with 20 iterative decoding. The gate count is 2M gates.
Original language | English |
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Title of host publication | 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers |
Pages | 101-104 |
Number of pages | 4 |
DOIs | |
Publication status | Published - 2007 |
Event | 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Hsinchu Duration: 2007 Apr 26 → 2007 Apr 28 |
Other
Other | 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 |
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City | Hsinchu |
Period | 07/4/26 → 07/4/28 |
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ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
High-throughput LDPC decoder for long code-length. / Ishikawa, Tatsuyuki; Shimizu, Kazunori; Ikenaga, Takeshi; Goto, Satoshi.
2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. p. 101-104 4027506.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - High-throughput LDPC decoder for long code-length
AU - Ishikawa, Tatsuyuki
AU - Shimizu, Kazunori
AU - Ikenaga, Takeshi
AU - Goto, Satoshi
PY - 2007
Y1 - 2007
N2 - We have designed and implemented the LDPC decoder with memory-reduction method to achieve high-throughput and practical hardware size for long code-length. The decoder decodes (3,6)-11520-rbit regular LDPC codes using modified minsum algorithm. The decoder achieves a throughput of 312 Mb/s at an operating frequency of 69 MHz with 20 iterative decoding. The gate count is 2M gates.
AB - We have designed and implemented the LDPC decoder with memory-reduction method to achieve high-throughput and practical hardware size for long code-length. The decoder decodes (3,6)-11520-rbit regular LDPC codes using modified minsum algorithm. The decoder achieves a throughput of 312 Mb/s at an operating frequency of 69 MHz with 20 iterative decoding. The gate count is 2M gates.
UR - http://www.scopus.com/inward/record.url?scp=34748907834&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=34748907834&partnerID=8YFLogxK
U2 - 10.1109/VDAT.2006.258134
DO - 10.1109/VDAT.2006.258134
M3 - Conference contribution
AN - SCOPUS:34748907834
SN - 1424401798
SN - 9781424401796
SP - 101
EP - 104
BT - 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers
ER -