High-throughput LDPC decoder for long code-length

Tatsuyuki Ishikawa; Kazunori Shimizu; Takeshi Ikenaga; Satoshi Goto

doi:10.1109/VDAT.2006.258134

High-throughput LDPC decoder for long code-length

Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

We have designed and implemented the LDPC decoder with memory-reduction method to achieve high-throughput and practical hardware size for long code-length. The decoder decodes (3,6)-11520-rbit regular LDPC codes using modified minsum algorithm. The decoder achieves a throughput of 312 Mb/s at an operating frequency of 69 MHz with 20 iterative decoding. The gate count is 2M gates.

Original language	English
Title of host publication	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers
Pages	101-104
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2006.258134
Publication status	Published - 2007 Oct 1
Event	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Hsinchu, Taiwan, Province of China Duration: 2007 Apr 26 → 2007 Apr 28

Publication series

Name	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

Conference

Conference	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006
Country	Taiwan, Province of China
City	Hsinchu
Period	07/4/26 → 07/4/28

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/VDAT.2006.258134

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Ishikawa, T., Shimizu, K., Ikenaga, T., & Goto, S. (2007). High-throughput LDPC decoder for long code-length. In 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers (pp. 101-104). [4027506] (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2006.258134

High-throughput LDPC decoder for long code-length. / Ishikawa, Tatsuyuki; Shimizu, Kazunori; Ikenaga, Takeshi; Goto, Satoshi.

2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. p. 101-104 4027506 (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ishikawa, T, Shimizu, K, Ikenaga, T & Goto, S 2007, High-throughput LDPC decoder for long code-length. in 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers., 4027506, 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers, pp. 101-104, 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006, Hsinchu, Taiwan, Province of China, 07/4/26. https://doi.org/10.1109/VDAT.2006.258134

Ishikawa T, Shimizu K, Ikenaga T, Goto S. High-throughput LDPC decoder for long code-length. In 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. p. 101-104. 4027506. (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2006.258134

Ishikawa, Tatsuyuki ; Shimizu, Kazunori ; Ikenaga, Takeshi ; Goto, Satoshi. / High-throughput LDPC decoder for long code-length. 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. pp. 101-104 (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers).

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abstract = "We have designed and implemented the LDPC decoder with memory-reduction method to achieve high-throughput and practical hardware size for long code-length. The decoder decodes (3,6)-11520-rbit regular LDPC codes using modified minsum algorithm. The decoder achieves a throughput of 312 Mb/s at an operating frequency of 69 MHz with 20 iterative decoding. The gate count is 2M gates.",

author = "Tatsuyuki Ishikawa and Kazunori Shimizu and Takeshi Ikenaga and Satoshi Goto",

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High-throughput LDPC decoder for long code-length

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