High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule

Wen Ji; Xing Li; Takeshi Ikenaga; Satoshi Goto

doi:10.1109/VDAT.2008.4542452

High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule

Wen Ji^*, Xing Li, Takeshi Ikenaga, Satoshi Goto

^*Corresponding author for this work

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, we propose a partially-parallel decoder architecture for irregular LDPC code targeting high throughput applications. The proposed decoder is based on a novel delta-value message-passing algorithm to facilitate the decoding throughput by removing redundant computations using the difference between the updated value and the original value. Techniques such as binary sorting, high performance pipelining are used to further speed up the message-passing procedure. The synthesis result in TSMC 0.18 CMOS technology shows that for (648,324) irregular LDPC code, our decoder can increase 8 times in throughput, which reaches 418 Mbps at the frequency of 200MHz.

Original language	English
Title of host publication	2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
Pages	220-223
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2008.4542452
Publication status	Published - 2008 Sept 5
Event	2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT - Hsinchu, Taiwan, Province of China Duration: 2008 Apr 23 → 2008 Apr 25

Publication series

Name	2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

Conference

Conference	2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	08/4/23 → 08/4/25

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/VDAT.2008.4542452

Cite this

Ji, W., Li, X., Ikenaga, T., & Goto, S. (2008). High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule. In 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT (pp. 220-223). [4542452] (2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT). https://doi.org/10.1109/VDAT.2008.4542452

High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule. / Ji, Wen; Li, Xing; Ikenaga, Takeshi et al.

2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. 2008. p. 220-223 4542452 (2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ji, W, Li, X, Ikenaga, T & Goto, S 2008, High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule. in 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT., 4542452, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT, pp. 220-223, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT, Hsinchu, Taiwan, Province of China, 08/4/23. https://doi.org/10.1109/VDAT.2008.4542452

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abstract = "In this paper, we propose a partially-parallel decoder architecture for irregular LDPC code targeting high throughput applications. The proposed decoder is based on a novel delta-value message-passing algorithm to facilitate the decoding throughput by removing redundant computations using the difference between the updated value and the original value. Techniques such as binary sorting, high performance pipelining are used to further speed up the message-passing procedure. The synthesis result in TSMC 0.18 CMOS technology shows that for (648,324) irregular LDPC code, our decoder can increase 8 times in throughput, which reaches 418 Mbps at the frequency of 200MHz.",

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AB - In this paper, we propose a partially-parallel decoder architecture for irregular LDPC code targeting high throughput applications. The proposed decoder is based on a novel delta-value message-passing algorithm to facilitate the decoding throughput by removing redundant computations using the difference between the updated value and the original value. Techniques such as binary sorting, high performance pipelining are used to further speed up the message-passing procedure. The synthesis result in TSMC 0.18 CMOS technology shows that for (648,324) irregular LDPC code, our decoder can increase 8 times in throughput, which reaches 418 Mbps at the frequency of 200MHz.

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High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule

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