High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule

Wen Ji, Xing Li, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we propose a partially-parallel decoder architecture for irregular LDPC code targeting high throughput applications. The proposed decoder is based on a novel delta-value message-passing algorithm to facilitate the decoding throughput by removing redundant computations using the difference between the updated value and the original value. Techniques such as binary sorting, high performance pipelining are used to further speed up the message-passing procedure. The synthesis result in TSMC 0.18 CMOS technology shows that for (648,324) irregular LDPC code, our decoder can increase 8 times in throughput, which reaches 418 Mbps at the frequency of 200MHz.

Original languageEnglish
Title of host publication2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
Pages220-223
Number of pages4
DOIs
Publication statusPublished - 2008
Event2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT - Hsinchu
Duration: 2008 Apr 232008 Apr 25

Other

Other2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
CityHsinchu
Period08/4/2308/4/25

Fingerprint

Message passing
Throughput
Parallel architectures
Sorting
Decoding

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Ji, W., Li, X., Ikenaga, T., & Goto, S. (2008). High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule. In 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT (pp. 220-223). [4542452] https://doi.org/10.1109/VDAT.2008.4542452

High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule. / Ji, Wen; Li, Xing; Ikenaga, Takeshi; Goto, Satoshi.

2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. 2008. p. 220-223 4542452.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ji, W, Li, X, Ikenaga, T & Goto, S 2008, High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule. in 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT., 4542452, pp. 220-223, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT, Hsinchu, 08/4/23. https://doi.org/10.1109/VDAT.2008.4542452
Ji W, Li X, Ikenaga T, Goto S. High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule. In 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. 2008. p. 220-223. 4542452 https://doi.org/10.1109/VDAT.2008.4542452
Ji, Wen ; Li, Xing ; Ikenaga, Takeshi ; Goto, Satoshi. / High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule. 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. 2008. pp. 220-223
@inproceedings{045c364aa1f947239a738c697e112884,
title = "High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule",
abstract = "In this paper, we propose a partially-parallel decoder architecture for irregular LDPC code targeting high throughput applications. The proposed decoder is based on a novel delta-value message-passing algorithm to facilitate the decoding throughput by removing redundant computations using the difference between the updated value and the original value. Techniques such as binary sorting, high performance pipelining are used to further speed up the message-passing procedure. The synthesis result in TSMC 0.18 CMOS technology shows that for (648,324) irregular LDPC code, our decoder can increase 8 times in throughput, which reaches 418 Mbps at the frequency of 200MHz.",
author = "Wen Ji and Xing Li and Takeshi Ikenaga and Satoshi Goto",
year = "2008",
doi = "10.1109/VDAT.2008.4542452",
language = "English",
isbn = "9781424416172",
pages = "220--223",
booktitle = "2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT",

}

TY - GEN

T1 - High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule

AU - Ji, Wen

AU - Li, Xing

AU - Ikenaga, Takeshi

AU - Goto, Satoshi

PY - 2008

Y1 - 2008

N2 - In this paper, we propose a partially-parallel decoder architecture for irregular LDPC code targeting high throughput applications. The proposed decoder is based on a novel delta-value message-passing algorithm to facilitate the decoding throughput by removing redundant computations using the difference between the updated value and the original value. Techniques such as binary sorting, high performance pipelining are used to further speed up the message-passing procedure. The synthesis result in TSMC 0.18 CMOS technology shows that for (648,324) irregular LDPC code, our decoder can increase 8 times in throughput, which reaches 418 Mbps at the frequency of 200MHz.

AB - In this paper, we propose a partially-parallel decoder architecture for irregular LDPC code targeting high throughput applications. The proposed decoder is based on a novel delta-value message-passing algorithm to facilitate the decoding throughput by removing redundant computations using the difference between the updated value and the original value. Techniques such as binary sorting, high performance pipelining are used to further speed up the message-passing procedure. The synthesis result in TSMC 0.18 CMOS technology shows that for (648,324) irregular LDPC code, our decoder can increase 8 times in throughput, which reaches 418 Mbps at the frequency of 200MHz.

UR - http://www.scopus.com/inward/record.url?scp=50649083950&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=50649083950&partnerID=8YFLogxK

U2 - 10.1109/VDAT.2008.4542452

DO - 10.1109/VDAT.2008.4542452

M3 - Conference contribution

AN - SCOPUS:50649083950

SN - 9781424416172

SP - 220

EP - 223

BT - 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

ER -