High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule

Wen Ji, Xing Li, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we propose a partially-parallel decoder architecture for irregular LDPC code targeting high throughput applications. The proposed decoder is based on a novel delta-value message-passing algorithm to facilitate the decoding throughput by removing redundant computations using the difference between the updated value and the original value. Techniques such as binary sorting, high performance pipelining are used to further speed up the message-passing procedure. The synthesis result in TSMC 0.18 CMOS technology shows that for (648,324) irregular LDPC code, our decoder can increase 8 times in throughput, which reaches 418 Mbps at the frequency of 200MHz.

Original languageEnglish
Title of host publication2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
Pages220-223
Number of pages4
DOIs
Publication statusPublished - 2008 Sep 5
Event2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT - Hsinchu, Taiwan, Province of China
Duration: 2008 Apr 232008 Apr 25

Publication series

Name2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

Conference

Conference2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
CountryTaiwan, Province of China
CityHsinchu
Period08/4/2308/4/25

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Ji, W., Li, X., Ikenaga, T., & Goto, S. (2008). High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule. In 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT (pp. 220-223). [4542452] (2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT). https://doi.org/10.1109/VDAT.2008.4542452