High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction

Tianruo Zhang, Shen Li, Guifen Tian, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Intra coding in H.264/AVC has significantly enhanced the video compression efficiency. However, computation complexity increases due to the rate-distortion (RD) based mode decision. This paper proposes a new fast mode decision algorithm in H.264/AVC intra prediction and its VLSI architecture. A new edge-detection pattern is proposed and both edge-detection technique and spatial mode prediction technique are combined together to reduce intra 4x4 candidate mode number from 9 to an average of 2.42. This algorithm is the only hardware-oriented algorithm which can reduce the number of 4x4 candidate mode to less than 4. VLSI architecture of intra mode decision module is designed with TSMC 0.18μm CMOS technology. The maximum frequency of 285MHz is achieved and 13.1k gates are required. High frequency, efficient processing cycle reduction and small area make this design to be an excellent accelerator for HDTV 1080p@30fps real time encoder.

Original languageEnglish
Title of host publication2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008
Pages1245-1249
Number of pages5
DOIs
Publication statusPublished - 2008
Event2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008 - Xiamen, Fujian Province
Duration: 2008 May 252008 May 27

Other

Other2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008
CityXiamen, Fujian Province
Period08/5/2508/5/27

Fingerprint

Throughput
Edge detection
High definition television
Image compression
Particle accelerators
Hardware
Processing

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Zhang, T., Li, S., Tian, G., Ikenaga, T., & Goto, S. (2008). High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction. In 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008 (pp. 1245-1249). [4657993] https://doi.org/10.1109/ICCCAS.2008.4657993

High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction. / Zhang, Tianruo; Li, Shen; Tian, Guifen; Ikenaga, Takeshi; Goto, Satoshi.

2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008. 2008. p. 1245-1249 4657993.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhang, T, Li, S, Tian, G, Ikenaga, T & Goto, S 2008, High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction. in 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008., 4657993, pp. 1245-1249, 2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008, Xiamen, Fujian Province, 08/5/25. https://doi.org/10.1109/ICCCAS.2008.4657993
Zhang T, Li S, Tian G, Ikenaga T, Goto S. High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction. In 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008. 2008. p. 1245-1249. 4657993 https://doi.org/10.1109/ICCCAS.2008.4657993
Zhang, Tianruo ; Li, Shen ; Tian, Guifen ; Ikenaga, Takeshi ; Goto, Satoshi. / High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction. 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008. 2008. pp. 1245-1249
@inproceedings{5c53b17f6573471d8c06a1b8c6efe4dd,
title = "High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction",
abstract = "Intra coding in H.264/AVC has significantly enhanced the video compression efficiency. However, computation complexity increases due to the rate-distortion (RD) based mode decision. This paper proposes a new fast mode decision algorithm in H.264/AVC intra prediction and its VLSI architecture. A new edge-detection pattern is proposed and both edge-detection technique and spatial mode prediction technique are combined together to reduce intra 4x4 candidate mode number from 9 to an average of 2.42. This algorithm is the only hardware-oriented algorithm which can reduce the number of 4x4 candidate mode to less than 4. VLSI architecture of intra mode decision module is designed with TSMC 0.18μm CMOS technology. The maximum frequency of 285MHz is achieved and 13.1k gates are required. High frequency, efficient processing cycle reduction and small area make this design to be an excellent accelerator for HDTV 1080p@30fps real time encoder.",
author = "Tianruo Zhang and Shen Li and Guifen Tian and Takeshi Ikenaga and Satoshi Goto",
year = "2008",
doi = "10.1109/ICCCAS.2008.4657993",
language = "English",
isbn = "9781424420636",
pages = "1245--1249",
booktitle = "2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008",

}

TY - GEN

T1 - High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction

AU - Zhang, Tianruo

AU - Li, Shen

AU - Tian, Guifen

AU - Ikenaga, Takeshi

AU - Goto, Satoshi

PY - 2008

Y1 - 2008

N2 - Intra coding in H.264/AVC has significantly enhanced the video compression efficiency. However, computation complexity increases due to the rate-distortion (RD) based mode decision. This paper proposes a new fast mode decision algorithm in H.264/AVC intra prediction and its VLSI architecture. A new edge-detection pattern is proposed and both edge-detection technique and spatial mode prediction technique are combined together to reduce intra 4x4 candidate mode number from 9 to an average of 2.42. This algorithm is the only hardware-oriented algorithm which can reduce the number of 4x4 candidate mode to less than 4. VLSI architecture of intra mode decision module is designed with TSMC 0.18μm CMOS technology. The maximum frequency of 285MHz is achieved and 13.1k gates are required. High frequency, efficient processing cycle reduction and small area make this design to be an excellent accelerator for HDTV 1080p@30fps real time encoder.

AB - Intra coding in H.264/AVC has significantly enhanced the video compression efficiency. However, computation complexity increases due to the rate-distortion (RD) based mode decision. This paper proposes a new fast mode decision algorithm in H.264/AVC intra prediction and its VLSI architecture. A new edge-detection pattern is proposed and both edge-detection technique and spatial mode prediction technique are combined together to reduce intra 4x4 candidate mode number from 9 to an average of 2.42. This algorithm is the only hardware-oriented algorithm which can reduce the number of 4x4 candidate mode to less than 4. VLSI architecture of intra mode decision module is designed with TSMC 0.18μm CMOS technology. The maximum frequency of 285MHz is achieved and 13.1k gates are required. High frequency, efficient processing cycle reduction and small area make this design to be an excellent accelerator for HDTV 1080p@30fps real time encoder.

UR - http://www.scopus.com/inward/record.url?scp=58149159193&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=58149159193&partnerID=8YFLogxK

U2 - 10.1109/ICCCAS.2008.4657993

DO - 10.1109/ICCCAS.2008.4657993

M3 - Conference contribution

SN - 9781424420636

SP - 1245

EP - 1249

BT - 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008

ER -