High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction

Tianruo Zhang; Shen Li; Guifen Tian; Takeshi Ikenaga; Satoshi Goto

doi:10.1109/ICCCAS.2008.4657993

High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction

Tianruo Zhang^*, Shen Li, Guifen Tian, Takeshi Ikenaga, Satoshi Goto

^*Corresponding author for this work

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

Intra coding in H.264/AVC has significantly enhanced the video compression efficiency. However, computation complexity increases due to the rate-distortion (RD) based mode decision. This paper proposes a new fast mode decision algorithm in H.264/AVC intra prediction and its VLSI architecture. A new edge-detection pattern is proposed and both edge-detection technique and spatial mode prediction technique are combined together to reduce intra 4x4 candidate mode number from 9 to an average of 2.42. This algorithm is the only hardware-oriented algorithm which can reduce the number of 4x4 candidate mode to less than 4. VLSI architecture of intra mode decision module is designed with TSMC 0.18μm CMOS technology. The maximum frequency of 285MHz is achieved and 13.1k gates are required. High frequency, efficient processing cycle reduction and small area make this design to be an excellent accelerator for HDTV 1080p@30fps real time encoder.

Original language	English
Title of host publication	2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008
Pages	1245-1249
Number of pages	5
DOIs	https://doi.org/10.1109/ICCCAS.2008.4657993
Publication status	Published - 2008 Dec 1
Event	2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008 - Xiamen, Fujian Province, China Duration: 2008 May 25 → 2008 May 27

Publication series

Name	2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008

Conference

Conference	2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008
Country/Territory	China
City	Xiamen, Fujian Province
Period	08/5/25 → 08/5/27

ASJC Scopus subject areas

Computer Networks and Communications
Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/ICCCAS.2008.4657993

Cite this

Zhang, T., Li, S., Tian, G., Ikenaga, T., & Goto, S. (2008). High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction. In 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008 (pp. 1245-1249). [4657993] (2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008). https://doi.org/10.1109/ICCCAS.2008.4657993

High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction. / Zhang, Tianruo; Li, Shen; Tian, Guifen et al.

2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008. 2008. p. 1245-1249 4657993 (2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zhang, T, Li, S, Tian, G, Ikenaga, T & Goto, S 2008, High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction. in 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008., 4657993, 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008, pp. 1245-1249, 2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008, Xiamen, Fujian Province, China, 08/5/25. https://doi.org/10.1109/ICCCAS.2008.4657993

Zhang T, Li S, Tian G, Ikenaga T, Goto S. High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction. In 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008. 2008. p. 1245-1249. 4657993. (2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008). doi: 10.1109/ICCCAS.2008.4657993

@inproceedings{5c53b17f6573471d8c06a1b8c6efe4dd,

title = "High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction",

abstract = "Intra coding in H.264/AVC has significantly enhanced the video compression efficiency. However, computation complexity increases due to the rate-distortion (RD) based mode decision. This paper proposes a new fast mode decision algorithm in H.264/AVC intra prediction and its VLSI architecture. A new edge-detection pattern is proposed and both edge-detection technique and spatial mode prediction technique are combined together to reduce intra 4x4 candidate mode number from 9 to an average of 2.42. This algorithm is the only hardware-oriented algorithm which can reduce the number of 4x4 candidate mode to less than 4. VLSI architecture of intra mode decision module is designed with TSMC 0.18μm CMOS technology. The maximum frequency of 285MHz is achieved and 13.1k gates are required. High frequency, efficient processing cycle reduction and small area make this design to be an excellent accelerator for HDTV 1080p@30fps real time encoder.",

author = "Tianruo Zhang and Shen Li and Guifen Tian and Takeshi Ikenaga and Satoshi Goto",

year = "2008",

month = dec,

day = "1",

doi = "10.1109/ICCCAS.2008.4657993",

language = "English",

isbn = "9781424420636",

series = "2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008",

pages = "1245--1249",

booktitle = "2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008",

note = "2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008 ; Conference date: 25-05-2008 Through 27-05-2008",

}

TY - GEN

T1 - High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction

AU - Zhang, Tianruo

AU - Li, Shen

AU - Tian, Guifen

AU - Ikenaga, Takeshi

AU - Goto, Satoshi

PY - 2008/12/1

Y1 - 2008/12/1

N2 - Intra coding in H.264/AVC has significantly enhanced the video compression efficiency. However, computation complexity increases due to the rate-distortion (RD) based mode decision. This paper proposes a new fast mode decision algorithm in H.264/AVC intra prediction and its VLSI architecture. A new edge-detection pattern is proposed and both edge-detection technique and spatial mode prediction technique are combined together to reduce intra 4x4 candidate mode number from 9 to an average of 2.42. This algorithm is the only hardware-oriented algorithm which can reduce the number of 4x4 candidate mode to less than 4. VLSI architecture of intra mode decision module is designed with TSMC 0.18μm CMOS technology. The maximum frequency of 285MHz is achieved and 13.1k gates are required. High frequency, efficient processing cycle reduction and small area make this design to be an excellent accelerator for HDTV 1080p@30fps real time encoder.

AB - Intra coding in H.264/AVC has significantly enhanced the video compression efficiency. However, computation complexity increases due to the rate-distortion (RD) based mode decision. This paper proposes a new fast mode decision algorithm in H.264/AVC intra prediction and its VLSI architecture. A new edge-detection pattern is proposed and both edge-detection technique and spatial mode prediction technique are combined together to reduce intra 4x4 candidate mode number from 9 to an average of 2.42. This algorithm is the only hardware-oriented algorithm which can reduce the number of 4x4 candidate mode to less than 4. VLSI architecture of intra mode decision module is designed with TSMC 0.18μm CMOS technology. The maximum frequency of 285MHz is achieved and 13.1k gates are required. High frequency, efficient processing cycle reduction and small area make this design to be an excellent accelerator for HDTV 1080p@30fps real time encoder.

UR - http://www.scopus.com/inward/record.url?scp=58149159193&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=58149159193&partnerID=8YFLogxK

U2 - 10.1109/ICCCAS.2008.4657993

DO - 10.1109/ICCCAS.2008.4657993

M3 - Conference contribution

AN - SCOPUS:58149159193

SN - 9781424420636

T3 - 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008

SP - 1245

EP - 1249

BT - 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008

T2 - 2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008

Y2 - 25 May 2008 through 27 May 2008

ER -

High throughput VLSI architecture of a fast mode decision algorithm for H.264/AVC intra prediction

Abstract

Publication series

Conference

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this