High-throughput von Neumann post-processing for random number generator

Ruilin Zhang, Sijia Chen, Chao Wan, Hirofumi Shinohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents the improvement and implementation of N bits Von Neumann (VN-N) post-processing technique, which is used to produce unbiased random bits sequence from biased one. Algorithm to realize general N bits VN-N and circuit level implementation of 4 bits VN-4 are shown. VN-4 achieved 40.6% output rate. A waiting strategy is further proposed to improve the output rate. VN-4+waiting and VN-8+waiting reached to 46.9% and 62.5% output rate, respectively. They are 1.88× and 2.50× improvements compared with original Von Neumann (VN-2) with 25.0%, respectively.

Original languageEnglish
Title of host publication2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-4
Number of pages4
ISBN (Electronic)9781538642603
DOIs
Publication statusPublished - 2018 Jun 5
Event2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 - Hsinchu, Taiwan, Province of China
Duration: 2018 Apr 162018 Apr 19

Other

Other2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
CountryTaiwan, Province of China
CityHsinchu
Period18/4/1618/4/19

Fingerprint

Random number Generator
Post-processing
High Throughput
Throughput
Output
Processing
Biased
Networks (circuits)

ASJC Scopus subject areas

  • Safety, Risk, Reliability and Quality
  • Control and Optimization
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Zhang, R., Chen, S., Wan, C., & Shinohara, H. (2018). High-throughput von Neumann post-processing for random number generator. In 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 (pp. 1-4). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2018.8373253

High-throughput von Neumann post-processing for random number generator. / Zhang, Ruilin; Chen, Sijia; Wan, Chao; Shinohara, Hirofumi.

2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-4.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhang, R, Chen, S, Wan, C & Shinohara, H 2018, High-throughput von Neumann post-processing for random number generator. in 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc., pp. 1-4, 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018, Hsinchu, Taiwan, Province of China, 18/4/16. https://doi.org/10.1109/VLSI-DAT.2018.8373253
Zhang R, Chen S, Wan C, Shinohara H. High-throughput von Neumann post-processing for random number generator. In 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1-4 https://doi.org/10.1109/VLSI-DAT.2018.8373253
Zhang, Ruilin ; Chen, Sijia ; Wan, Chao ; Shinohara, Hirofumi. / High-throughput von Neumann post-processing for random number generator. 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 1-4
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