Highly flexible row and column redundancy and cycle time adaptive read data path for double data rate synchronous memories

Kiyohiro Furutani, Takeshi Hamamoto, Takeo Miki, Masaya Nakano, Takashi Kono, Shigeru Kikuda, Yasuhiro Konishi, Tsutomu Yoshihara

    Research output: Contribution to journalArticle

    1 Citation (Scopus)

    Abstract

    This paper describes two circuit techniques useful for the design of high density and high speed low cost double data rate memories. One is a highly flexible row and column redundancy circuit which allows the division of flexible row redundancy unit into multiple column redundancy unit for higher flexibility, with a new test mode circuit which enables the use of the finer pitch laser fuse. Another is a compact read data path which allows the smooth data flow without wait time in the high frequency operation with less area penalty. These circuit techniques achieved the compact chip size with the cell efficiency of 60.6% and the high band-width of 400 MHz operation with CL=2.5.

    Original languageEnglish
    Pages (from-to)255-262
    Number of pages8
    JournalIEICE Transactions on Electronics
    VolumeE88-C
    Issue number2
    Publication statusPublished - 2005

    Keywords

    • DRAM
    • High density
    • High speed
    • Redundancy

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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  • Cite this

    Furutani, K., Hamamoto, T., Miki, T., Nakano, M., Kono, T., Kikuda, S., Konishi, Y., & Yoshihara, T. (2005). Highly flexible row and column redundancy and cycle time adaptive read data path for double data rate synchronous memories. IEICE Transactions on Electronics, E88-C(2), 255-262.