Abstract
The main features of the process are as follows: 1) adoption of epitaxial-growth wafer; 2) bird's beak-reduced LOCOS isolation; 3) highly reliable memory cell capacitor with 10 nm SiO//2; 4) low resistivity TiSi//2 polycide gate electrode; 5) Al-Si-Ti interconnection with low temperature planarization of the underlying layer; and 6) 1. 2- mu m pattern formation by a 5:1 step and repeat aligner followed by reactive ion etching. A highly reliable 1M multiplied by 1 dynamic MOS memory was successfully fabricated.
| Original language | English |
|---|---|
| Title of host publication | Technical Digest - International Electron Devices Meeting |
| Publisher | IEEE |
| Pages | 647-650 |
| Number of pages | 4 |
| Publication status | Published - 1984 |
| Externally published | Yes |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
HIGHLY RELIABLE N-MOS PROCESS FOR ONE MEGABIT DYNAMIC RANDOM ACCESS MEMORY. / Matsukawa, T.; Inuishi, Masahide; Mitsuhashi, J.; Hirayama, M.; Tsukamoto, K.; Uoya, S.; Yoshihara, T.; Nakata, H.
Technical Digest - International Electron Devices Meeting. IEEE, 1984. p. 647-650.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - HIGHLY RELIABLE N-MOS PROCESS FOR ONE MEGABIT DYNAMIC RANDOM ACCESS MEMORY.
AU - Matsukawa, T.
AU - Inuishi, Masahide
AU - Mitsuhashi, J.
AU - Hirayama, M.
AU - Tsukamoto, K.
AU - Uoya, S.
AU - Yoshihara, T.
AU - Nakata, H.
PY - 1984
Y1 - 1984
N2 - The main features of the process are as follows: 1) adoption of epitaxial-growth wafer; 2) bird's beak-reduced LOCOS isolation; 3) highly reliable memory cell capacitor with 10 nm SiO//2; 4) low resistivity TiSi//2 polycide gate electrode; 5) Al-Si-Ti interconnection with low temperature planarization of the underlying layer; and 6) 1. 2- mu m pattern formation by a 5:1 step and repeat aligner followed by reactive ion etching. A highly reliable 1M multiplied by 1 dynamic MOS memory was successfully fabricated.
AB - The main features of the process are as follows: 1) adoption of epitaxial-growth wafer; 2) bird's beak-reduced LOCOS isolation; 3) highly reliable memory cell capacitor with 10 nm SiO//2; 4) low resistivity TiSi//2 polycide gate electrode; 5) Al-Si-Ti interconnection with low temperature planarization of the underlying layer; and 6) 1. 2- mu m pattern formation by a 5:1 step and repeat aligner followed by reactive ion etching. A highly reliable 1M multiplied by 1 dynamic MOS memory was successfully fabricated.
UR - http://www.scopus.com/inward/record.url?scp=0021640302&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0021640302&partnerID=8YFLogxK
M3 - Conference contribution
SP - 647
EP - 650
BT - Technical Digest - International Electron Devices Meeting
PB - IEEE
ER -