HIGHLY RELIABLE N-MOS PROCESS FOR ONE MEGABIT DYNAMIC RANDOM ACCESS MEMORY.

T. Matsukawa; M. Inuishi; J. Mitsuhashi; M. Hirayama; K. Tsukamoto; S. Uoya; T. Yoshihara; H. Nakata

HIGHLY RELIABLE N-MOS PROCESS FOR ONE MEGABIT DYNAMIC RANDOM ACCESS MEMORY.

T. Matsukawa^*, M. Inuishi, J. Mitsuhashi, M. Hirayama, K. Tsukamoto, S. Uoya, T. Yoshihara, H. Nakata

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

2 Citations (Scopus)

Abstract

The main features of the process are as follows: 1) adoption of epitaxial-growth wafer; 2) bird's beak-reduced LOCOS isolation; 3) highly reliable memory cell capacitor with 10 nm SiO//2; 4) low resistivity TiSi//2 polycide gate electrode; 5) Al-Si-Ti interconnection with low temperature planarization of the underlying layer; and 6) 1. 2- mu m pattern formation by a 5:1 step and repeat aligner followed by reactive ion etching. A highly reliable 1M multiplied by 1 dynamic MOS memory was successfully fabricated.

Original language	English
Pages (from-to)	647-650
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
Publication status	Published - 1984 Dec 1
Externally published	Yes

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Cite this

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title = "HIGHLY RELIABLE N-MOS PROCESS FOR ONE MEGABIT DYNAMIC RANDOM ACCESS MEMORY.",

abstract = "The main features of the process are as follows: 1) adoption of epitaxial-growth wafer; 2) bird's beak-reduced LOCOS isolation; 3) highly reliable memory cell capacitor with 10 nm SiO//2; 4) low resistivity TiSi//2 polycide gate electrode; 5) Al-Si-Ti interconnection with low temperature planarization of the underlying layer; and 6) 1. 2- mu m pattern formation by a 5:1 step and repeat aligner followed by reactive ion etching. A highly reliable 1M multiplied by 1 dynamic MOS memory was successfully fabricated.",

author = "T. Matsukawa and M. Inuishi and J. Mitsuhashi and M. Hirayama and K. Tsukamoto and S. Uoya and T. Yoshihara and H. Nakata",

year = "1984",

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AU - Matsukawa, T.

AU - Inuishi, M.

AU - Mitsuhashi, J.

AU - Hirayama, M.

AU - Tsukamoto, K.

AU - Uoya, S.

AU - Yoshihara, T.

AU - Nakata, H.

PY - 1984/12/1

Y1 - 1984/12/1

N2 - The main features of the process are as follows: 1) adoption of epitaxial-growth wafer; 2) bird's beak-reduced LOCOS isolation; 3) highly reliable memory cell capacitor with 10 nm SiO//2; 4) low resistivity TiSi//2 polycide gate electrode; 5) Al-Si-Ti interconnection with low temperature planarization of the underlying layer; and 6) 1. 2- mu m pattern formation by a 5:1 step and repeat aligner followed by reactive ion etching. A highly reliable 1M multiplied by 1 dynamic MOS memory was successfully fabricated.

AB - The main features of the process are as follows: 1) adoption of epitaxial-growth wafer; 2) bird's beak-reduced LOCOS isolation; 3) highly reliable memory cell capacitor with 10 nm SiO//2; 4) low resistivity TiSi//2 polycide gate electrode; 5) Al-Si-Ti interconnection with low temperature planarization of the underlying layer; and 6) 1. 2- mu m pattern formation by a 5:1 step and repeat aligner followed by reactive ion etching. A highly reliable 1M multiplied by 1 dynamic MOS memory was successfully fabricated.

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M3 - Conference article

AN - SCOPUS:0021640302

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EP - 650

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

SN - 0163-1918

ER -

HIGHLY RELIABLE N-MOS PROCESS FOR ONE MEGABIT DYNAMIC RANDOM ACCESS MEMORY.

Abstract

ASJC Scopus subject areas

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