HIGHLY RELIABLE N-MOS PROCESS FOR ONE MEGABIT DYNAMIC RANDOM ACCESS MEMORY.

T. Matsukawa, Masahide Inuishi, J. Mitsuhashi, M. Hirayama, K. Tsukamoto, S. Uoya, T. Yoshihara, H. Nakata

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The main features of the process are as follows: 1) adoption of epitaxial-growth wafer; 2) bird's beak-reduced LOCOS isolation; 3) highly reliable memory cell capacitor with 10 nm SiO//2; 4) low resistivity TiSi//2 polycide gate electrode; 5) Al-Si-Ti interconnection with low temperature planarization of the underlying layer; and 6) 1. 2- mu m pattern formation by a 5:1 step and repeat aligner followed by reactive ion etching. A highly reliable 1M multiplied by 1 dynamic MOS memory was successfully fabricated.

Original languageEnglish
Title of host publicationTechnical Digest - International Electron Devices Meeting
PublisherIEEE
Pages647-650
Number of pages4
Publication statusPublished - 1984
Externally publishedYes

Fingerprint

Data storage equipment
Reactive ion etching
Birds
Epitaxial growth
Capacitors
Electrodes
Temperature

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Matsukawa, T., Inuishi, M., Mitsuhashi, J., Hirayama, M., Tsukamoto, K., Uoya, S., ... Nakata, H. (1984). HIGHLY RELIABLE N-MOS PROCESS FOR ONE MEGABIT DYNAMIC RANDOM ACCESS MEMORY. In Technical Digest - International Electron Devices Meeting (pp. 647-650). IEEE.

HIGHLY RELIABLE N-MOS PROCESS FOR ONE MEGABIT DYNAMIC RANDOM ACCESS MEMORY. / Matsukawa, T.; Inuishi, Masahide; Mitsuhashi, J.; Hirayama, M.; Tsukamoto, K.; Uoya, S.; Yoshihara, T.; Nakata, H.

Technical Digest - International Electron Devices Meeting. IEEE, 1984. p. 647-650.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Matsukawa, T, Inuishi, M, Mitsuhashi, J, Hirayama, M, Tsukamoto, K, Uoya, S, Yoshihara, T & Nakata, H 1984, HIGHLY RELIABLE N-MOS PROCESS FOR ONE MEGABIT DYNAMIC RANDOM ACCESS MEMORY. in Technical Digest - International Electron Devices Meeting. IEEE, pp. 647-650.
Matsukawa T, Inuishi M, Mitsuhashi J, Hirayama M, Tsukamoto K, Uoya S et al. HIGHLY RELIABLE N-MOS PROCESS FOR ONE MEGABIT DYNAMIC RANDOM ACCESS MEMORY. In Technical Digest - International Electron Devices Meeting. IEEE. 1984. p. 647-650
Matsukawa, T. ; Inuishi, Masahide ; Mitsuhashi, J. ; Hirayama, M. ; Tsukamoto, K. ; Uoya, S. ; Yoshihara, T. ; Nakata, H. / HIGHLY RELIABLE N-MOS PROCESS FOR ONE MEGABIT DYNAMIC RANDOM ACCESS MEMORY. Technical Digest - International Electron Devices Meeting. IEEE, 1984. pp. 647-650
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AU - Nakata, H.

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