Abstract
Networks-on-Chip (NoCs) offers considerable performance improvement to Chip Multi-Processors (CMPs). As the communication between processors on NoC increases, its system performance faces a severe challenge in congestion issues. Adaptive routing algorithm for NoCs provides a variety of path options, thus, it has fantastic potential to achieve better traffic distribution across the network by avoiding the congested regions. An excellent output selection method can realize the potential of adaptive routing algorithm as highly as possible. Therefore, designing an efficient output selection method is highly desirable. Conventional output selection methods only consider local information (buffer vacancy) or global information (path diversity) separately, which makes them difficult to spread traffic to different paths for load balance. In this paper, we propose an efficient output selection method integrating global information of path diversity and local information of buffer vacancy, to solve congestion problem in NoCs.
Original language | English |
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Title of host publication | Proceedings - International SoC Design Conference 2017, ISOCC 2017 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 125-126 |
Number of pages | 2 |
ISBN (Electronic) | 9781538622858 |
DOIs | |
Publication status | Published - 2018 May 29 |
Event | 14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of Duration: 2017 Nov 5 → 2017 Nov 8 |
Other
Other | 14th International SoC Design Conference, ISOCC 2017 |
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Country/Territory | Korea, Republic of |
City | Seoul |
Period | 17/11/5 → 17/11/8 |
Keywords
- Adaptive routing method
- Network-on-chip
- Output selection method
- Path diversity
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials