HyMacs: Hybrid memory access optimization based on custom-instruction scheduling

Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents an efficient hybrid memory access optimization system called HyMacs, which integrates the hardware and software optimization strategies in the embedded system design. First, HyMacs features a pre-configuration stage which is equipped with a memory configuration algorithm to satisfy area constraints. Then a custom instruction generation process is integrated in the system via a seedgrowth algorithm under the intelligent guide functions. The custom instruction benefits to the reduction of the whole memory access latency and thus relieves the burden of system through hardware mode. Finally, a data-dependencydriven scheduling algorithm is also integrated to compress the whole latency through access mode conversion. We have tested the system on a set of commonly used benchmarks, and compared the results with the previous memory access system MACCESS-opt proposed in DAC'05. The experimental results indicate 20% enhancement obtained for the total memory access latency reduction compared with MACCESS-opt, where the custom instruction generation and scheduling contribute about 15% and 5% respectively.

Original languageEnglish
Title of host publicationProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Pages89-94
Number of pages6
DOIs
Publication statusPublished - 2008
EventGLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008 - Orlando, FL
Duration: 2008 Mar 42008 Mar 6

Other

OtherGLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008
CityOrlando, FL
Period08/3/408/3/6

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Keywords

  • ASIP
  • CAD algorithm
  • Hardware/software co-design

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Zhao, K., Bian, J., Dong, S., Song, Y., & Goto, S. (2008). HyMacs: Hybrid memory access optimization based on custom-instruction scheduling. In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI (pp. 89-94) https://doi.org/10.1145/1366110.1366133