Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    Alpha blending is one of image synthesis techniques, which synthesizes a new image by summing up weighted input images and realizes transparent effect. In this paper, we focus on alpha blending using selector logics and implement it on an FPGA board. By applying selector logics to the alpha blending operation, its total product terms are decreased and thus a circuit size and circuit delay are improved simultaneously. In our implementation, original pixel values are stored into a memory on the FPGA board and then a new pixel value is synthesized based on input transmittance factors. We realize approximately 23% speed-up and 8% area reduction simultaneously using selector-logic based alpha blending.

    Original languageEnglish
    Title of host publicationProceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    ISBN (Electronic)9781479984831
    DOIs
    Publication statusPublished - 2016 Jul 19
    Event11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China
    Duration: 2015 Nov 32015 Nov 6

    Other

    Other11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
    CountryChina
    CityChengdu
    Period15/11/315/11/6

    Fingerprint

    Field programmable gate arrays (FPGA)
    Networks (circuits)
    Pixels
    Delay circuits
    Data storage equipment

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

    Cite this

    Igarashi, K., Yanagisawa, M., & Togawa, N. (2016). Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation. In Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015 [7517027] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASICON.2015.7517027

    Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation. / Igarashi, Keita; Yanagisawa, Masao; Togawa, Nozomu.

    Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 2016. 7517027.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Igarashi, K, Yanagisawa, M & Togawa, N 2016, Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation. in Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015., 7517027, Institute of Electrical and Electronics Engineers Inc., 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015, Chengdu, China, 15/11/3. https://doi.org/10.1109/ASICON.2015.7517027
    Igarashi K, Yanagisawa M, Togawa N. Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation. In Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc. 2016. 7517027 https://doi.org/10.1109/ASICON.2015.7517027
    Igarashi, Keita ; Yanagisawa, Masao ; Togawa, Nozomu. / Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation. Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 2016.
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