Impact of 0.10 μm SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology

Y. Hirano, T. Matsumoto, S. Maeda, T. Iwamatsu, T. Kunikiyo, K. Nii, K. Yamamoto, Y. Yamaguchi, T. Ipposhi, S. Maegawa, Masahide Inuishi

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Abstract

A hybrid-trench-isolation (HTI) technology is proposed to overcome the scaling limitations caused by the difficulty of gate thinning and increased soft error rate at the 0.1 μm era. It is revealed that a significant speed improvement against bulk is achieved by using the body-tied structure without floating-body-related speed deterioration. A two-order reduction in the soft error rate for an HTI-SOI 4M-bit SRAM was demonstrated as compared with bulk one. Moreover, it is presented that full trench isolation in the HTI offers excellent isolation characteristics to realize the one-chip integration of analog and digital LSI's. It is concluded that SOI technology with the HTI structure is one of the solutions against the scaling limitations.

Original languageEnglish
Pages (from-to)467-470
Number of pages4
JournalUnknown Journal
Publication statusPublished - 2000
Externally publishedYes

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Hirano, Y., Matsumoto, T., Maeda, S., Iwamatsu, T., Kunikiyo, T., Nii, K., Yamamoto, K., Yamaguchi, Y., Ipposhi, T., Maegawa, S., & Inuishi, M. (2000). Impact of 0.10 μm SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology. Unknown Journal, 467-470.