Impact of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications

S. Maeda, Y. Wada, K. Yamamoto, H. Komurasaki, T. Matsumoto, Y. Hirano, T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, K. Ueda, K. Mashiko, S. Maegawa, Masahide Inuishi

Research output: Contribution to journalArticle

12 Citations (Scopus)

Abstract

A 0.18 μm silicon on insulator (SOI) CMOS using hybrid trench isolation with high resistivity substrate (HRS) is proposed and revealed its impact on high performance embedded RF/analog applications. Using this technology, advantages of SOI MOSFETs due to the reduction of power loss is proven. Then, excellent body-fixing capability of this SOI MOSFET and high-quality on-chip inductance is demonstrated for RF/analog LSIs.

Original languageEnglish
Pages (from-to)154-155
Number of pages2
JournalUnknown Journal
Publication statusPublished - 2000
Externally publishedYes

Fingerprint

isolation
CMOS
insulators
analogs
Silicon
electrical resistivity
silicon
Substrates
field effect transistors
large scale integration
power loss
inductance
Inductance
fixing
chips

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Impact of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications. / Maeda, S.; Wada, Y.; Yamamoto, K.; Komurasaki, H.; Matsumoto, T.; Hirano, Y.; Iwamatsu, T.; Yamaguchi, Y.; Ipposhi, T.; Ueda, K.; Mashiko, K.; Maegawa, S.; Inuishi, Masahide.

In: Unknown Journal, 2000, p. 154-155.

Research output: Contribution to journalArticle

Maeda, S, Wada, Y, Yamamoto, K, Komurasaki, H, Matsumoto, T, Hirano, Y, Iwamatsu, T, Yamaguchi, Y, Ipposhi, T, Ueda, K, Mashiko, K, Maegawa, S & Inuishi, M 2000, 'Impact of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications', Unknown Journal, pp. 154-155.
Maeda, S. ; Wada, Y. ; Yamamoto, K. ; Komurasaki, H. ; Matsumoto, T. ; Hirano, Y. ; Iwamatsu, T. ; Yamaguchi, Y. ; Ipposhi, T. ; Ueda, K. ; Mashiko, K. ; Maegawa, S. ; Inuishi, Masahide. / Impact of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications. In: Unknown Journal. 2000 ; pp. 154-155.
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AU - Hirano, Y.

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AU - Ueda, K.

AU - Mashiko, K.

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AU - Inuishi, Masahide

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