Impact of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications

S. Maeda, Y. Wada, K. Yamamoto, H. Komurasaki, T. Matsumoto, Y. Hirano, T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, K. Ueda, K. Mashiko, S. Maegawa, M. Inuishi

Research output: Contribution to journalConference article

12 Citations (Scopus)

Abstract

A 0.18 μm silicon on insulator (SOI) CMOS using hybrid trench isolation with high resistivity substrate (HRS) is proposed and revealed its impact on high performance embedded RF/analog applications. Using this technology, advantages of SOI MOSFETs due to the reduction of power loss is proven. Then, excellent body-fixing capability of this SOI MOSFET and high-quality on-chip inductance is demonstrated for RF/analog LSIs.

Original languageEnglish
Pages (from-to)154-155
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
Publication statusPublished - 2000 Jan 1
Event2000 Symposium on VLSI Technology - Honolulu, HI, USA
Duration: 2000 Jun 132000 Jun 15

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Maeda, S., Wada, Y., Yamamoto, K., Komurasaki, H., Matsumoto, T., Hirano, Y., Iwamatsu, T., Yamaguchi, Y., Ipposhi, T., Ueda, K., Mashiko, K., Maegawa, S., & Inuishi, M. (2000). Impact of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications. Digest of Technical Papers - Symposium on VLSI Technology, 154-155.