Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond

T. Yamashita, K. Shiga, T. Hayashi, H. Umeda, H. Oda, T. Eimori, Masahide Inuishi, Y. Ohji, K. Eriguchi, K. Nakanishi, H. Nakaoka, T. Yamada, M. Nakamura, I. Miyanaga, A. Kajiya, M. Kubota, M. Ogura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

For scaled CMOSFETs, it becomes much more difficult to ensure sufficient reliability of gate-oxide film, since power supply voltage is not scaled proportionally with gate-oxide. As well as the increase of the electrical stress that put on the gate-oxide, miniaturization effect should be cared. This paper demonstrates the performance of 65-nm node CMOSFETs, focused on gate oxide reliability, which is found to become crucial issue for short-channel pMOSFETs. Boron penetration from S/D-extension is found to increase gate leakage current and degrade gate oxide integrity. Fabrication process that suppresses the boron penetration is discussed, and optimized transistor characteristics for low operational power (LOP) and low standby power (LSTP) devices are presented.

Original languageEnglish
Title of host publicationIMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages123-124
Number of pages2
ISBN (Electronic)0780384237, 9780780384231
DOIs
Publication statusPublished - 2004
Externally publishedYes
Event2nd International Meeting for Future of Electron Devices, Kansai, IMFEDK 2004 - Kyoto, Japan
Duration: 2004 Jul 262004 Jul 28

Other

Other2nd International Meeting for Future of Electron Devices, Kansai, IMFEDK 2004
CountryJapan
CityKyoto
Period04/7/2604/7/28

Fingerprint

Leakage currents
Boron
Oxides
Oxide films
Transistors
Fabrication
Electric potential

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Yamashita, T., Shiga, K., Hayashi, T., Umeda, H., Oda, H., Eimori, T., ... Ogura, M. (2004). Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond. In IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai (pp. 123-124). [1566439] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IMFEDK.2004.1566439

Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond. / Yamashita, T.; Shiga, K.; Hayashi, T.; Umeda, H.; Oda, H.; Eimori, T.; Inuishi, Masahide; Ohji, Y.; Eriguchi, K.; Nakanishi, K.; Nakaoka, H.; Yamada, T.; Nakamura, M.; Miyanaga, I.; Kajiya, A.; Kubota, M.; Ogura, M.

IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai. Institute of Electrical and Electronics Engineers Inc., 2004. p. 123-124 1566439.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yamashita, T, Shiga, K, Hayashi, T, Umeda, H, Oda, H, Eimori, T, Inuishi, M, Ohji, Y, Eriguchi, K, Nakanishi, K, Nakaoka, H, Yamada, T, Nakamura, M, Miyanaga, I, Kajiya, A, Kubota, M & Ogura, M 2004, Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond. in IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai., 1566439, Institute of Electrical and Electronics Engineers Inc., pp. 123-124, 2nd International Meeting for Future of Electron Devices, Kansai, IMFEDK 2004, Kyoto, Japan, 04/7/26. https://doi.org/10.1109/IMFEDK.2004.1566439
Yamashita T, Shiga K, Hayashi T, Umeda H, Oda H, Eimori T et al. Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond. In IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai. Institute of Electrical and Electronics Engineers Inc. 2004. p. 123-124. 1566439 https://doi.org/10.1109/IMFEDK.2004.1566439
Yamashita, T. ; Shiga, K. ; Hayashi, T. ; Umeda, H. ; Oda, H. ; Eimori, T. ; Inuishi, Masahide ; Ohji, Y. ; Eriguchi, K. ; Nakanishi, K. ; Nakaoka, H. ; Yamada, T. ; Nakamura, M. ; Miyanaga, I. ; Kajiya, A. ; Kubota, M. ; Ogura, M. / Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond. IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai. Institute of Electrical and Electronics Engineers Inc., 2004. pp. 123-124
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abstract = "For scaled CMOSFETs, it becomes much more difficult to ensure sufficient reliability of gate-oxide film, since power supply voltage is not scaled proportionally with gate-oxide. As well as the increase of the electrical stress that put on the gate-oxide, miniaturization effect should be cared. This paper demonstrates the performance of 65-nm node CMOSFETs, focused on gate oxide reliability, which is found to become crucial issue for short-channel pMOSFETs. Boron penetration from S/D-extension is found to increase gate leakage current and degrade gate oxide integrity. Fabrication process that suppresses the boron penetration is discussed, and optimized transistor characteristics for low operational power (LOP) and low standby power (LSTP) devices are presented.",
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AU - Yamashita, T.

AU - Shiga, K.

AU - Hayashi, T.

AU - Umeda, H.

AU - Oda, H.

AU - Eimori, T.

AU - Inuishi, Masahide

AU - Ohji, Y.

AU - Eriguchi, K.

AU - Nakanishi, K.

AU - Nakaoka, H.

AU - Yamada, T.

AU - Nakamura, M.

AU - Miyanaga, I.

AU - Kajiya, A.

AU - Kubota, M.

AU - Ogura, M.

PY - 2004

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AB - For scaled CMOSFETs, it becomes much more difficult to ensure sufficient reliability of gate-oxide film, since power supply voltage is not scaled proportionally with gate-oxide. As well as the increase of the electrical stress that put on the gate-oxide, miniaturization effect should be cared. This paper demonstrates the performance of 65-nm node CMOSFETs, focused on gate oxide reliability, which is found to become crucial issue for short-channel pMOSFETs. Boron penetration from S/D-extension is found to increase gate leakage current and degrade gate oxide integrity. Fabrication process that suppresses the boron penetration is discussed, and optimized transistor characteristics for low operational power (LOP) and low standby power (LSTP) devices are presented.

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