“Implementation of Hardware Engine for Real-Time KLT Tracker”

Takahiro Sakayori; Takeshi Ikenaga

doi:10.11371/iieej.38.656

“Implementation of Hardware Engine for Real-Time KLT Tracker”

Takahiro Sakayori, Takeshi Ikenaga

Graduate School of Information, Production and Systems

Research output: Contribution to journal › Article

1 Citation (Scopus)

Abstract

A real-time object tracking becomes more and more important in a wide variety of vehicle or surveillance camera systems. This paper focuses on implementation of a hardware engine for a real-time KLT Tracker (Kanade-Lucas-Tomasi) which is known as a robust object tracking algorithm. The proposed architecture includes stream data and parallel processing schemes for high performance. Furthermore, a memory I/F based on FIFO and image block buffer enable to reduce a memory access delay. Experimental results based on FPGA show that the proposed engine can attain 9 ms @ 100 MHz for a 640 × 480 image with 100 feature points.

Original language	English
Pages (from-to)	656-663
Number of pages	8
Journal	Journal of the Institute of Image Electronics Engineers of Japan
Volume	38
Issue number	5
DOIs	https://doi.org/10.11371/iieej.38.656
Publication status	Published - 2009

Keywords

FPGA
Hardware Engine
KLT Tracker

ASJC Scopus subject areas

Computer Science (miscellaneous)
Electrical and Electronic Engineering

Access to Document

10.11371/iieej.38.656

Fingerprint Dive into the research topics of '“Implementation of Hardware Engine for Real-Time KLT Tracker”'. Together they form a unique fingerprint.

Cite this

Sakayori, T., & Ikenaga, T. (2009). “Implementation of Hardware Engine for Real-Time KLT Tracker”. Journal of the Institute of Image Electronics Engineers of Japan, 38(5), 656-663. https://doi.org/10.11371/iieej.38.656

@article{735a37333fad4bd78ba59adb4e8d79e9,

title = "“Implementation of Hardware Engine for Real-Time KLT Tracker”",

abstract = "A real-time object tracking becomes more and more important in a wide variety of vehicle or surveillance camera systems. This paper focuses on implementation of a hardware engine for a real-time KLT Tracker (Kanade-Lucas-Tomasi) which is known as a robust object tracking algorithm. The proposed architecture includes stream data and parallel processing schemes for high performance. Furthermore, a memory I/F based on FIFO and image block buffer enable to reduce a memory access delay. Experimental results based on FPGA show that the proposed engine can attain 9 ms @ 100 MHz for a 640 × 480 image with 100 feature points.",

keywords = "FPGA, Hardware Engine, KLT Tracker",

author = "Takahiro Sakayori and Takeshi Ikenaga",

year = "2009",

doi = "10.11371/iieej.38.656",

language = "English",

volume = "38",

pages = "656--663",

journal = "Journal of the Institute of Image Electronics Engineers of Japan",

issn = "0285-9831",

publisher = "Institute of Image Electronics Engineers of Japan",

number = "5",

}

TY - JOUR

T1 - “Implementation of Hardware Engine for Real-Time KLT Tracker”

AU - Sakayori, Takahiro

AU - Ikenaga, Takeshi

PY - 2009

Y1 - 2009

N2 - A real-time object tracking becomes more and more important in a wide variety of vehicle or surveillance camera systems. This paper focuses on implementation of a hardware engine for a real-time KLT Tracker (Kanade-Lucas-Tomasi) which is known as a robust object tracking algorithm. The proposed architecture includes stream data and parallel processing schemes for high performance. Furthermore, a memory I/F based on FIFO and image block buffer enable to reduce a memory access delay. Experimental results based on FPGA show that the proposed engine can attain 9 ms @ 100 MHz for a 640 × 480 image with 100 feature points.

AB - A real-time object tracking becomes more and more important in a wide variety of vehicle or surveillance camera systems. This paper focuses on implementation of a hardware engine for a real-time KLT Tracker (Kanade-Lucas-Tomasi) which is known as a robust object tracking algorithm. The proposed architecture includes stream data and parallel processing schemes for high performance. Furthermore, a memory I/F based on FIFO and image block buffer enable to reduce a memory access delay. Experimental results based on FPGA show that the proposed engine can attain 9 ms @ 100 MHz for a 640 × 480 image with 100 feature points.

KW - FPGA

KW - Hardware Engine

KW - KLT Tracker

UR - http://www.scopus.com/inward/record.url?scp=85017235192&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85017235192&partnerID=8YFLogxK

U2 - 10.11371/iieej.38.656

DO - 10.11371/iieej.38.656

M3 - Article

AN - SCOPUS:85017235192

VL - 38

SP - 656

EP - 663

JO - Journal of the Institute of Image Electronics Engineers of Japan

JF - Journal of the Institute of Image Electronics Engineers of Japan

SN - 0285-9831

IS - 5

ER -