Improved delay-matching bus routing by using multi-layers

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Recently, signal propagation delay in VLSI or PCB becomes a very critical problem due to the increasing clock frequency, where signal delay should be adjusted to meet the requirement of the delay time. The delay can be roughly estimated by the net length. While, due to the circuit complexity and the high density of integration, a single layer routing may not be enough for delay estimation. In recent research, there's a highly efficient algorithm for length matching bus routing for signal delay. However, it doesn't put the high density of integration into consideration. The purpose of this paper is to route several nets by using multiple layers on a high density board to meet the signal delay requirement, even if there exist obstacles in the routing area. Previous research put focus on the single layer routing without considering the complexity and density of the board. In this paper, the complexity and density are taken into account. In our proposed algorithm, the routing area is divided into subareas to solve the problem efficiently, some searching vertices will be set in advance and nets can be assigned to the proper layers to avoid obstacles. After the net assignment, path generation is executed. Then, some optimizations are made to meet the signal delay for each net. Finally, the routing paths of nets which satisfy the delay constraint are determined. Experimental results show that our proposed method is highly effective and efficient.

Original languageEnglish
Title of host publicationICEP-IAAC 2015 - 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages708-713
Number of pages6
ISBN (Print)9784904090138
DOIs
Publication statusPublished - 2015 May 20
Event2015 International Conference on Electronic Packaging and iMAPS All Asia Conference, ICEP-IAAC 2015 - Kyoto, Japan
Duration: 2015 Apr 142015 Apr 17

Other

Other2015 International Conference on Electronic Packaging and iMAPS All Asia Conference, ICEP-IAAC 2015
CountryJapan
CityKyoto
Period15/4/1415/4/17

Fingerprint

Polychlorinated biphenyls
Clocks
Time delay
Networks (circuits)

Keywords

  • delay matching
  • multiple layers
  • routing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Tian, Y., & Watanabe, T. (2015). Improved delay-matching bus routing by using multi-layers. In ICEP-IAAC 2015 - 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference (pp. 708-713). [7111103] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICEP-IAAC.2015.7111103

Improved delay-matching bus routing by using multi-layers. / Tian, Yang; Watanabe, Takahiro.

ICEP-IAAC 2015 - 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference. Institute of Electrical and Electronics Engineers Inc., 2015. p. 708-713 7111103.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tian, Y & Watanabe, T 2015, Improved delay-matching bus routing by using multi-layers. in ICEP-IAAC 2015 - 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference., 7111103, Institute of Electrical and Electronics Engineers Inc., pp. 708-713, 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference, ICEP-IAAC 2015, Kyoto, Japan, 15/4/14. https://doi.org/10.1109/ICEP-IAAC.2015.7111103
Tian Y, Watanabe T. Improved delay-matching bus routing by using multi-layers. In ICEP-IAAC 2015 - 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference. Institute of Electrical and Electronics Engineers Inc. 2015. p. 708-713. 7111103 https://doi.org/10.1109/ICEP-IAAC.2015.7111103
Tian, Yang ; Watanabe, Takahiro. / Improved delay-matching bus routing by using multi-layers. ICEP-IAAC 2015 - 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 708-713
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