Improvement of thermal fatigue properties of Sn-Ag-Cu lead-free solder interconnects on casio's wafer-level packages based on morphology and grain boundary character

S. Terashima*, T. Kohno, A. Mizusawa, K. Arai, O. Okada, T. Wakabayashi, M. Tanaka, K. Tatsumi

*Corresponding author for this work

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30 Citations (Scopus)

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