In-situ timing monitoring methods for variation-resilient designs

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    With technology scaling, process, voltage, and temperature (PVT) variations pose great challenges on integrated circuit designs. Conventionally, LSI circuits are designed by adding pessimistic timing margin to guarantee 'always correct' operations even under worst-case conditions. However, due to the increasing PVT variations, unacceptable larger design guard band should be reserved to avoid timing errors on critical paths of circuits, which will therefore lead to very inefficient designs in terms of power and performance. For this reason, in-situ timing monitoring technique has gained great research interest. In this paper, we will review existing variation-resilient design techniques with particular emphasis on in-situ timing monitoring techniques including both detection and prediction-based methods. The effectiveness of in-situ timing monitoring techniques will be discussed. Finally, we show an example of in-situ timing monitoring technique called STEP with applications to general pipeline designs.

    Original languageEnglish
    Title of host publicationIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages735-738
    Number of pages4
    Volume2015-February
    EditionFebruary
    DOIs
    Publication statusPublished - 2015 Feb 5
    Event2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 - Ishigaki Island, Okinawa, Japan
    Duration: 2014 Nov 172014 Nov 20

    Other

    Other2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
    CountryJapan
    CityIshigaki Island, Okinawa
    Period14/11/1714/11/20

    Fingerprint

    Monitoring
    LSI circuits
    Electric potential
    Pipelines
    Temperature
    Networks (circuits)
    Integrated circuit design

    Keywords

    • design margin
    • timing error detection
    • timing error prediction
    • timing monitoring
    • variation

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Shi, Y., & Togawa, N. (2015). In-situ timing monitoring methods for variation-resilient designs. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS (February ed., Vol. 2015-February, pp. 735-738). [7032886] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2014.7032886

    In-situ timing monitoring methods for variation-resilient designs. / Shi, Youhua; Togawa, Nozomu.

    IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Vol. 2015-February February. ed. Institute of Electrical and Electronics Engineers Inc., 2015. p. 735-738 7032886.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Shi, Y & Togawa, N 2015, In-situ timing monitoring methods for variation-resilient designs. in IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. February edn, vol. 2015-February, 7032886, Institute of Electrical and Electronics Engineers Inc., pp. 735-738, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014, Ishigaki Island, Okinawa, Japan, 14/11/17. https://doi.org/10.1109/APCCAS.2014.7032886
    Shi Y, Togawa N. In-situ timing monitoring methods for variation-resilient designs. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. February ed. Vol. 2015-February. Institute of Electrical and Electronics Engineers Inc. 2015. p. 735-738. 7032886 https://doi.org/10.1109/APCCAS.2014.7032886
    Shi, Youhua ; Togawa, Nozomu. / In-situ timing monitoring methods for variation-resilient designs. IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Vol. 2015-February February. ed. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 735-738
    @inproceedings{1fc5ab90f8fd4de18e5a1fa59dfea0c3,
    title = "In-situ timing monitoring methods for variation-resilient designs",
    abstract = "With technology scaling, process, voltage, and temperature (PVT) variations pose great challenges on integrated circuit designs. Conventionally, LSI circuits are designed by adding pessimistic timing margin to guarantee 'always correct' operations even under worst-case conditions. However, due to the increasing PVT variations, unacceptable larger design guard band should be reserved to avoid timing errors on critical paths of circuits, which will therefore lead to very inefficient designs in terms of power and performance. For this reason, in-situ timing monitoring technique has gained great research interest. In this paper, we will review existing variation-resilient design techniques with particular emphasis on in-situ timing monitoring techniques including both detection and prediction-based methods. The effectiveness of in-situ timing monitoring techniques will be discussed. Finally, we show an example of in-situ timing monitoring technique called STEP with applications to general pipeline designs.",
    keywords = "design margin, timing error detection, timing error prediction, timing monitoring, variation",
    author = "Youhua Shi and Nozomu Togawa",
    year = "2015",
    month = "2",
    day = "5",
    doi = "10.1109/APCCAS.2014.7032886",
    language = "English",
    volume = "2015-February",
    pages = "735--738",
    booktitle = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",
    publisher = "Institute of Electrical and Electronics Engineers Inc.",
    edition = "February",

    }

    TY - GEN

    T1 - In-situ timing monitoring methods for variation-resilient designs

    AU - Shi, Youhua

    AU - Togawa, Nozomu

    PY - 2015/2/5

    Y1 - 2015/2/5

    N2 - With technology scaling, process, voltage, and temperature (PVT) variations pose great challenges on integrated circuit designs. Conventionally, LSI circuits are designed by adding pessimistic timing margin to guarantee 'always correct' operations even under worst-case conditions. However, due to the increasing PVT variations, unacceptable larger design guard band should be reserved to avoid timing errors on critical paths of circuits, which will therefore lead to very inefficient designs in terms of power and performance. For this reason, in-situ timing monitoring technique has gained great research interest. In this paper, we will review existing variation-resilient design techniques with particular emphasis on in-situ timing monitoring techniques including both detection and prediction-based methods. The effectiveness of in-situ timing monitoring techniques will be discussed. Finally, we show an example of in-situ timing monitoring technique called STEP with applications to general pipeline designs.

    AB - With technology scaling, process, voltage, and temperature (PVT) variations pose great challenges on integrated circuit designs. Conventionally, LSI circuits are designed by adding pessimistic timing margin to guarantee 'always correct' operations even under worst-case conditions. However, due to the increasing PVT variations, unacceptable larger design guard band should be reserved to avoid timing errors on critical paths of circuits, which will therefore lead to very inefficient designs in terms of power and performance. For this reason, in-situ timing monitoring technique has gained great research interest. In this paper, we will review existing variation-resilient design techniques with particular emphasis on in-situ timing monitoring techniques including both detection and prediction-based methods. The effectiveness of in-situ timing monitoring techniques will be discussed. Finally, we show an example of in-situ timing monitoring technique called STEP with applications to general pipeline designs.

    KW - design margin

    KW - timing error detection

    KW - timing error prediction

    KW - timing monitoring

    KW - variation

    UR - http://www.scopus.com/inward/record.url?scp=84937889817&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=84937889817&partnerID=8YFLogxK

    U2 - 10.1109/APCCAS.2014.7032886

    DO - 10.1109/APCCAS.2014.7032886

    M3 - Conference contribution

    VL - 2015-February

    SP - 735

    EP - 738

    BT - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

    PB - Institute of Electrical and Electronics Engineers Inc.

    ER -