In-situ timing monitoring methods for variation-resilient designs

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

With technology scaling, process, voltage, and temperature (PVT) variations pose great challenges on integrated circuit designs. Conventionally, LSI circuits are designed by adding pessimistic timing margin to guarantee 'always correct' operations even under worst-case conditions. However, due to the increasing PVT variations, unacceptable larger design guard band should be reserved to avoid timing errors on critical paths of circuits, which will therefore lead to very inefficient designs in terms of power and performance. For this reason, in-situ timing monitoring technique has gained great research interest. In this paper, we will review existing variation-resilient design techniques with particular emphasis on in-situ timing monitoring techniques including both detection and prediction-based methods. The effectiveness of in-situ timing monitoring techniques will be discussed. Finally, we show an example of in-situ timing monitoring technique called STEP with applications to general pipeline designs.

Original languageEnglish
Title of host publication2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages735-738
Number of pages4
EditionFebruary
ISBN (Electronic)9781479952304
DOIs
Publication statusPublished - 2015 Feb 5
Event2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 - Ishigaki Island, Okinawa, Japan
Duration: 2014 Nov 172014 Nov 20

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
NumberFebruary
Volume2015-February

Other

Other2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
CountryJapan
CityIshigaki Island, Okinawa
Period14/11/1714/11/20

Keywords

  • design margin
  • timing error detection
  • timing error prediction
  • timing monitoring
  • variation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Shi, Y., & Togawa, N. (2015). In-situ timing monitoring methods for variation-resilient designs. In 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 (February ed., pp. 735-738). [7032886] (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; Vol. 2015-February, No. February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2014.7032886