Increase of crosstalk noise due to imbalanced threshold voltage between nMOS and pMOS in subthreshold logic circuits

Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

An abnormal increase in crosstalk noise in subthreshold logic circuits is observed for the first time. When the threshold voltages (VTH) of nMOS and pMOS are imbalanced and the on-resistance of the aggressor driver is much lower than that of the victim driver, large crosstalk noise is observed, because the on-resistance has an exponential dependence on VTH in the subthreshold region being different from normal voltage operations. A simple crosstalk noise model is also proposed and verified with SPICE simulations. In a crosstalk noise test chip with a 1.5-mm interconnect in 40-nm CMOS at a power supply voltage (V DD) of 0.3 V, the measured noise amplitude increases from 32% of V DD to 71% of V DD, when V TH imbalance is realized by tuning body bias in pMOS. This body bias tuning can be used to mitigate the crosstalk problem in chip designs. For noise induced by a rising edge, the noise becomes largest under the slow-nMOS/fast-pMOS corner condition, while for noise induced by a falling edge, the noise becomes largest under the fast-nMOS/slow-pMOS corner condition, which is explained by the proposed model.

Original languageEnglish
Article number6515395
Pages (from-to)1986-1994
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume48
Issue number8
DOIs
Publication statusPublished - 2013
Externally publishedYes

Fingerprint

Logic circuits
Crosstalk
Threshold voltage
Tuning
Electric potential
SPICE

Keywords

  • Crosstalk
  • Manufacturing variability
  • Noise measurement
  • Signal integrity
  • Subthreshold circuit

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Increase of crosstalk noise due to imbalanced threshold voltage between nMOS and pMOS in subthreshold logic circuits. / Fuketa, Hiroshi; Takahashi, Ryo; Takamiya, Makoto; Nomura, Masahiro; Shinohara, Hirofumi; Sakurai, Takayasu.

In: IEEE Journal of Solid-State Circuits, Vol. 48, No. 8, 6515395, 2013, p. 1986-1994.

Research output: Contribution to journalArticle

Fuketa, Hiroshi ; Takahashi, Ryo ; Takamiya, Makoto ; Nomura, Masahiro ; Shinohara, Hirofumi ; Sakurai, Takayasu. / Increase of crosstalk noise due to imbalanced threshold voltage between nMOS and pMOS in subthreshold logic circuits. In: IEEE Journal of Solid-State Circuits. 2013 ; Vol. 48, No. 8. pp. 1986-1994.
@article{566c3b2dfd704ee2b51431d44b3373f3,
title = "Increase of crosstalk noise due to imbalanced threshold voltage between nMOS and pMOS in subthreshold logic circuits",
abstract = "An abnormal increase in crosstalk noise in subthreshold logic circuits is observed for the first time. When the threshold voltages (VTH) of nMOS and pMOS are imbalanced and the on-resistance of the aggressor driver is much lower than that of the victim driver, large crosstalk noise is observed, because the on-resistance has an exponential dependence on VTH in the subthreshold region being different from normal voltage operations. A simple crosstalk noise model is also proposed and verified with SPICE simulations. In a crosstalk noise test chip with a 1.5-mm interconnect in 40-nm CMOS at a power supply voltage (V DD) of 0.3 V, the measured noise amplitude increases from 32{\%} of V DD to 71{\%} of V DD, when V TH imbalance is realized by tuning body bias in pMOS. This body bias tuning can be used to mitigate the crosstalk problem in chip designs. For noise induced by a rising edge, the noise becomes largest under the slow-nMOS/fast-pMOS corner condition, while for noise induced by a falling edge, the noise becomes largest under the fast-nMOS/slow-pMOS corner condition, which is explained by the proposed model.",
keywords = "Crosstalk, Manufacturing variability, Noise measurement, Signal integrity, Subthreshold circuit",
author = "Hiroshi Fuketa and Ryo Takahashi and Makoto Takamiya and Masahiro Nomura and Hirofumi Shinohara and Takayasu Sakurai",
year = "2013",
doi = "10.1109/JSSC.2013.2258831",
language = "English",
volume = "48",
pages = "1986--1994",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "8",

}

TY - JOUR

T1 - Increase of crosstalk noise due to imbalanced threshold voltage between nMOS and pMOS in subthreshold logic circuits

AU - Fuketa, Hiroshi

AU - Takahashi, Ryo

AU - Takamiya, Makoto

AU - Nomura, Masahiro

AU - Shinohara, Hirofumi

AU - Sakurai, Takayasu

PY - 2013

Y1 - 2013

N2 - An abnormal increase in crosstalk noise in subthreshold logic circuits is observed for the first time. When the threshold voltages (VTH) of nMOS and pMOS are imbalanced and the on-resistance of the aggressor driver is much lower than that of the victim driver, large crosstalk noise is observed, because the on-resistance has an exponential dependence on VTH in the subthreshold region being different from normal voltage operations. A simple crosstalk noise model is also proposed and verified with SPICE simulations. In a crosstalk noise test chip with a 1.5-mm interconnect in 40-nm CMOS at a power supply voltage (V DD) of 0.3 V, the measured noise amplitude increases from 32% of V DD to 71% of V DD, when V TH imbalance is realized by tuning body bias in pMOS. This body bias tuning can be used to mitigate the crosstalk problem in chip designs. For noise induced by a rising edge, the noise becomes largest under the slow-nMOS/fast-pMOS corner condition, while for noise induced by a falling edge, the noise becomes largest under the fast-nMOS/slow-pMOS corner condition, which is explained by the proposed model.

AB - An abnormal increase in crosstalk noise in subthreshold logic circuits is observed for the first time. When the threshold voltages (VTH) of nMOS and pMOS are imbalanced and the on-resistance of the aggressor driver is much lower than that of the victim driver, large crosstalk noise is observed, because the on-resistance has an exponential dependence on VTH in the subthreshold region being different from normal voltage operations. A simple crosstalk noise model is also proposed and verified with SPICE simulations. In a crosstalk noise test chip with a 1.5-mm interconnect in 40-nm CMOS at a power supply voltage (V DD) of 0.3 V, the measured noise amplitude increases from 32% of V DD to 71% of V DD, when V TH imbalance is realized by tuning body bias in pMOS. This body bias tuning can be used to mitigate the crosstalk problem in chip designs. For noise induced by a rising edge, the noise becomes largest under the slow-nMOS/fast-pMOS corner condition, while for noise induced by a falling edge, the noise becomes largest under the fast-nMOS/slow-pMOS corner condition, which is explained by the proposed model.

KW - Crosstalk

KW - Manufacturing variability

KW - Noise measurement

KW - Signal integrity

KW - Subthreshold circuit

UR - http://www.scopus.com/inward/record.url?scp=84880917643&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84880917643&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2013.2258831

DO - 10.1109/JSSC.2013.2258831

M3 - Article

AN - SCOPUS:84880917643

VL - 48

SP - 1986

EP - 1994

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 8

M1 - 6515395

ER -