Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits

Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Abnormal increase of the crosstalk noise in the sub-threshold logic circuits is found for the first time. When the threshold voltages (V TH) of nMOS and pMOS are imbalanced and the on-resistance of the aggressor driver is much lower than that of the victim driver, the large crosstalk noise is observed, because the on-resistance has an exponential dependence on VTH in the sub-threshold circuits. In this paper, the large crosstalk noise due to the imbalanced VTH is measured. A new crosstalk noise model is also proposed and verified with SPICE simulations. In a crosstalk noise test chip with 1.5-mm wire in a 40-nm CMOS at the power supply voltage (VDD) of 0.3V, the measured noise amplitude increases from 32% of VDD to 71% of VDD, when the imbalanced V TH is realized by tuning a body bias in pMOS. In the worst case fast-nMOS/slow-pMOS corner simulations, the noise amplitude increases from 47% of VDD to 68% of VDD, when VDD is reduced from 1.1V to 0.3V, which is explained by the proposed model.

Original languageEnglish
Title of host publicationProceedings of the Custom Integrated Circuits Conference
DOIs
Publication statusPublished - 2012
Externally publishedYes
Event34th Annual Custom Integrated Circuits Conference, CICC 2012 - San Jose, CA, United States
Duration: 2012 Sep 92012 Sep 12

Other

Other34th Annual Custom Integrated Circuits Conference, CICC 2012
CountryUnited States
CitySan Jose, CA
Period12/9/912/9/12

Fingerprint

Threshold logic
Logic circuits
Crosstalk
Threshold voltage
SPICE
Tuning
Wire
Networks (circuits)
Electric potential

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Fuketa, H., Takahashi, R., Takamiya, M., Nomura, M., Shinohara, H., & Sakurai, T. (2012). Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. In Proceedings of the Custom Integrated Circuits Conference [6330689] https://doi.org/10.1109/CICC.2012.6330689

Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. / Fuketa, Hiroshi; Takahashi, Ryo; Takamiya, Makoto; Nomura, Masahiro; Shinohara, Hirofumi; Sakurai, Takayasu.

Proceedings of the Custom Integrated Circuits Conference. 2012. 6330689.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fuketa, H, Takahashi, R, Takamiya, M, Nomura, M, Shinohara, H & Sakurai, T 2012, Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. in Proceedings of the Custom Integrated Circuits Conference., 6330689, 34th Annual Custom Integrated Circuits Conference, CICC 2012, San Jose, CA, United States, 12/9/9. https://doi.org/10.1109/CICC.2012.6330689
Fuketa H, Takahashi R, Takamiya M, Nomura M, Shinohara H, Sakurai T. Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. In Proceedings of the Custom Integrated Circuits Conference. 2012. 6330689 https://doi.org/10.1109/CICC.2012.6330689
Fuketa, Hiroshi ; Takahashi, Ryo ; Takamiya, Makoto ; Nomura, Masahiro ; Shinohara, Hirofumi ; Sakurai, Takayasu. / Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. Proceedings of the Custom Integrated Circuits Conference. 2012.
@inproceedings{96b01a05df304331b8f0d4cc03bd81e7,
title = "Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits",
abstract = "Abnormal increase of the crosstalk noise in the sub-threshold logic circuits is found for the first time. When the threshold voltages (V TH) of nMOS and pMOS are imbalanced and the on-resistance of the aggressor driver is much lower than that of the victim driver, the large crosstalk noise is observed, because the on-resistance has an exponential dependence on VTH in the sub-threshold circuits. In this paper, the large crosstalk noise due to the imbalanced VTH is measured. A new crosstalk noise model is also proposed and verified with SPICE simulations. In a crosstalk noise test chip with 1.5-mm wire in a 40-nm CMOS at the power supply voltage (VDD) of 0.3V, the measured noise amplitude increases from 32{\%} of VDD to 71{\%} of VDD, when the imbalanced V TH is realized by tuning a body bias in pMOS. In the worst case fast-nMOS/slow-pMOS corner simulations, the noise amplitude increases from 47{\%} of VDD to 68{\%} of VDD, when VDD is reduced from 1.1V to 0.3V, which is explained by the proposed model.",
author = "Hiroshi Fuketa and Ryo Takahashi and Makoto Takamiya and Masahiro Nomura and Hirofumi Shinohara and Takayasu Sakurai",
year = "2012",
doi = "10.1109/CICC.2012.6330689",
language = "English",
isbn = "9781467315555",
booktitle = "Proceedings of the Custom Integrated Circuits Conference",

}

TY - GEN

T1 - Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits

AU - Fuketa, Hiroshi

AU - Takahashi, Ryo

AU - Takamiya, Makoto

AU - Nomura, Masahiro

AU - Shinohara, Hirofumi

AU - Sakurai, Takayasu

PY - 2012

Y1 - 2012

N2 - Abnormal increase of the crosstalk noise in the sub-threshold logic circuits is found for the first time. When the threshold voltages (V TH) of nMOS and pMOS are imbalanced and the on-resistance of the aggressor driver is much lower than that of the victim driver, the large crosstalk noise is observed, because the on-resistance has an exponential dependence on VTH in the sub-threshold circuits. In this paper, the large crosstalk noise due to the imbalanced VTH is measured. A new crosstalk noise model is also proposed and verified with SPICE simulations. In a crosstalk noise test chip with 1.5-mm wire in a 40-nm CMOS at the power supply voltage (VDD) of 0.3V, the measured noise amplitude increases from 32% of VDD to 71% of VDD, when the imbalanced V TH is realized by tuning a body bias in pMOS. In the worst case fast-nMOS/slow-pMOS corner simulations, the noise amplitude increases from 47% of VDD to 68% of VDD, when VDD is reduced from 1.1V to 0.3V, which is explained by the proposed model.

AB - Abnormal increase of the crosstalk noise in the sub-threshold logic circuits is found for the first time. When the threshold voltages (V TH) of nMOS and pMOS are imbalanced and the on-resistance of the aggressor driver is much lower than that of the victim driver, the large crosstalk noise is observed, because the on-resistance has an exponential dependence on VTH in the sub-threshold circuits. In this paper, the large crosstalk noise due to the imbalanced VTH is measured. A new crosstalk noise model is also proposed and verified with SPICE simulations. In a crosstalk noise test chip with 1.5-mm wire in a 40-nm CMOS at the power supply voltage (VDD) of 0.3V, the measured noise amplitude increases from 32% of VDD to 71% of VDD, when the imbalanced V TH is realized by tuning a body bias in pMOS. In the worst case fast-nMOS/slow-pMOS corner simulations, the noise amplitude increases from 47% of VDD to 68% of VDD, when VDD is reduced from 1.1V to 0.3V, which is explained by the proposed model.

UR - http://www.scopus.com/inward/record.url?scp=84869444394&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84869444394&partnerID=8YFLogxK

U2 - 10.1109/CICC.2012.6330689

DO - 10.1109/CICC.2012.6330689

M3 - Conference contribution

SN - 9781467315555

BT - Proceedings of the Custom Integrated Circuits Conference

ER -