Incremental placement and global routing algorithm for field-programmable gate arrays

Nozomu Togawa, Kayoko Hagi, Masao Yanagisawa, Tatsuo Ohtsuki

    Research output: Chapter in Book/Report/Conference proceedingChapter

    4 Citations (Scopus)

    Abstract

    Rapid system prototyping is one of the main applications for field-programmable gate arrays (FPGAs). At the stage of rapid system prototyping, design specifications can often be changed since they cannot always be determined completely. In this paper, layout design change is focused on and a layout reconfiguration algorithm is proposed for FPGAs. In layout reconfiguration, the main problem is to add LUTs to initial layouts. Our algorithm consists of two steps: For given placement and global routing of LUTs, Step 1 places an added LUT with allowing that the position of the added LUT may overlap that of a preplaced LUT; Then Step 2 moves preplaced LUTs to their adjacent positions so that the overlap of the LUT positions can be resolved. Global routes are updated corresponding to reconfiguration of placement. The algorithm keeps routing congestion small by evaluating global routes directly both in Steps 1 and 2. Especially in Step 2, if the minimum number of preplaced LUTs are moved to their adjacent positions, our algorithm minimizes routing congestion. Experimental results demonstrate the effectiveness and efficiency of the algorithm.

    Original languageEnglish
    Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
    Place of PublicationPiscataway, NJ, United States
    PublisherIEEE
    Pages519-526
    Number of pages8
    Publication statusPublished - 1998
    EventProceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) - Yokohama, Jpn
    Duration: 1998 Feb 101998 Feb 13

    Other

    OtherProceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98)
    CityYokohama, Jpn
    Period98/2/1098/2/13

    Fingerprint

    Routing algorithms
    Field programmable gate arrays (FPGA)
    Specifications

    ASJC Scopus subject areas

    • Engineering(all)

    Cite this

    Togawa, N., Hagi, K., Yanagisawa, M., & Ohtsuki, T. (1998). Incremental placement and global routing algorithm for field-programmable gate arrays. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 519-526). Piscataway, NJ, United States: IEEE.

    Incremental placement and global routing algorithm for field-programmable gate arrays. / Togawa, Nozomu; Hagi, Kayoko; Yanagisawa, Masao; Ohtsuki, Tatsuo.

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States : IEEE, 1998. p. 519-526.

    Research output: Chapter in Book/Report/Conference proceedingChapter

    Togawa, N, Hagi, K, Yanagisawa, M & Ohtsuki, T 1998, Incremental placement and global routing algorithm for field-programmable gate arrays. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. IEEE, Piscataway, NJ, United States, pp. 519-526, Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98), Yokohama, Jpn, 98/2/10.
    Togawa N, Hagi K, Yanagisawa M, Ohtsuki T. Incremental placement and global routing algorithm for field-programmable gate arrays. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States: IEEE. 1998. p. 519-526
    Togawa, Nozomu ; Hagi, Kayoko ; Yanagisawa, Masao ; Ohtsuki, Tatsuo. / Incremental placement and global routing algorithm for field-programmable gate arrays. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States : IEEE, 1998. pp. 519-526
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