Instruction set and functional unit synthesis for SIMD processor cores

Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)

    Abstract

    This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a timing constraint, the proposed algorithm synthesizes an area-optimized processor core with optimal SIMD functional units. It also synthesizes a SIMD instruction set. The input initial assembly code is assumed to run on a full-resource SIMD processor (virtual processor) which has all the possible SIMD functional units. In our algorithm, we introduce the SIMD operation decomposition and apply it to the initial assembly code and the full-resource SIMD processor. By gradually reducing SIMD operations or decomposing SIMD operations, we can finally find a processor core with small area under the given timing constraint. The promising experimental results are also shown.

    Original languageEnglish
    Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
    Pages743-750
    Number of pages8
    Publication statusPublished - 2004
    EventProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama
    Duration: 2004 Jan 272004 Jan 30

    Other

    OtherProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004
    CityYokohama
    Period04/1/2704/1/30

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    Decomposition

    ASJC Scopus subject areas

    • Engineering(all)

    Cite this

    Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M., & Ohtsuki, T. (2004). Instruction set and functional unit synthesis for SIMD processor cores. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 743-750)

    Instruction set and functional unit synthesis for SIMD processor cores. / Togawa, Nozomu; Tachikake, Koichi; Miyaoka, Yuichiro; Yanagisawa, Masao; Ohtsuki, Tatsuo.

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2004. p. 743-750.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Togawa, N, Tachikake, K, Miyaoka, Y, Yanagisawa, M & Ohtsuki, T 2004, Instruction set and functional unit synthesis for SIMD processor cores. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. pp. 743-750, Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004, Yokohama, 04/1/27.
    Togawa N, Tachikake K, Miyaoka Y, Yanagisawa M, Ohtsuki T. Instruction set and functional unit synthesis for SIMD processor cores. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2004. p. 743-750
    Togawa, Nozomu ; Tachikake, Koichi ; Miyaoka, Yuichiro ; Yanagisawa, Masao ; Ohtsuki, Tatsuo. / Instruction set and functional unit synthesis for SIMD processor cores. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2004. pp. 743-750
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