Instruction set and functional unit synthesis for SIMD processor cores

Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki

Research output: Contribution to conferencePaperpeer-review

3 Citations (Scopus)

Abstract

This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a timing constraint, the proposed algorithm synthesizes an area-optimized processor core with optimal SIMD functional units. It also synthesizes a SIMD instruction set. The input initial assembly code is assumed to run on a full-resource SIMD processor (virtual processor) which has all the possible SIMD functional units. In our algorithm, we introduce the SIMD operation decomposition and apply it to the initial assembly code and the full-resource SIMD processor. By gradually reducing SIMD operations or decomposing SIMD operations, we can finally find a processor core with small area under the given timing constraint. The promising experimental results are also shown.

Original languageEnglish
Pages743-750
Number of pages8
Publication statusPublished - 2004 Jun 1
EventProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan
Duration: 2004 Jan 272004 Jan 30

Conference

ConferenceProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004
CountryJapan
CityYokohama
Period04/1/2704/1/30

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Instruction set and functional unit synthesis for SIMD processor cores'. Together they form a unique fingerprint.

Cite this