Interconnect design strategy: Structures, repeaters and materials toward 0.1 μm ULSIs with a Giga-hertz clock operation

Shuji Takahashi, Masato Edahiro, Yoshihiro Hayashi

Research output: Contribution to journalConference article

20 Citations (Scopus)

Abstract

With the interconnect analysis using the LSI performance prediction model, the local and global line structures are optimized from 0.18 to 0.1 μm generations. The chip size enlargement with the wider global line pitch and the inserted repeaters are calculated. It is cleared that both low-ρ and low-k materials are necessary to restrain the chip size enlargement in 0.1 μm generation.

Original languageEnglish
Pages (from-to)833-836
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 1998
Externally publishedYes
EventProceedings of the 1998 IEEE International Electron Devices Meeting - San Francisco, CA, USA
Duration: 1998 Dec 61998 Dec 9

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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