Interconnect design strategy: Structures, repeaters and materials toward 0.1 μm ULSIs with a Giga-hertz clock operation

Shuji Takahashi; Masato Edahiro; Yoshihiro Hayashi

Interconnect design strategy: Structures, repeaters and materials toward 0.1 μm ULSIs with a Giga-hertz clock operation

Shuji Takahashi^*, Masato Edahiro, Yoshihiro Hayashi

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

20 Citations (Scopus)

Abstract

With the interconnect analysis using the LSI performance prediction model, the local and global line structures are optimized from 0.18 to 0.1 μm generations. The chip size enlargement with the wider global line pitch and the inserted repeaters are calculated. It is cleared that both low-ρ and low-k materials are necessary to restrain the chip size enlargement in 0.1 μm generation.

Original language	English
Pages (from-to)	833-836
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
Publication status	Published - 1998
Externally published	Yes
Event	Proceedings of the 1998 IEEE International Electron Devices Meeting - San Francisco, CA, USA Duration: 1998 Dec 6 → 1998 Dec 9

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Cite this

@article{6e0105f499844510acd9fa4620da63c7,

title = "Interconnect design strategy: Structures, repeaters and materials toward 0.1 μm ULSIs with a Giga-hertz clock operation",

abstract = "With the interconnect analysis using the LSI performance prediction model, the local and global line structures are optimized from 0.18 to 0.1 μm generations. The chip size enlargement with the wider global line pitch and the inserted repeaters are calculated. It is cleared that both low-ρ and low-k materials are necessary to restrain the chip size enlargement in 0.1 μm generation.",

author = "Shuji Takahashi and Masato Edahiro and Yoshihiro Hayashi",

year = "1998",

language = "English",

pages = "833--836",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1998 IEEE International Electron Devices Meeting ; Conference date: 06-12-1998 Through 09-12-1998",

}

TY - JOUR

T1 - Interconnect design strategy

T2 - Proceedings of the 1998 IEEE International Electron Devices Meeting

AU - Takahashi, Shuji

AU - Edahiro, Masato

AU - Hayashi, Yoshihiro

PY - 1998

Y1 - 1998

N2 - With the interconnect analysis using the LSI performance prediction model, the local and global line structures are optimized from 0.18 to 0.1 μm generations. The chip size enlargement with the wider global line pitch and the inserted repeaters are calculated. It is cleared that both low-ρ and low-k materials are necessary to restrain the chip size enlargement in 0.1 μm generation.

AB - With the interconnect analysis using the LSI performance prediction model, the local and global line structures are optimized from 0.18 to 0.1 μm generations. The chip size enlargement with the wider global line pitch and the inserted repeaters are calculated. It is cleared that both low-ρ and low-k materials are necessary to restrain the chip size enlargement in 0.1 μm generation.

UR - http://www.scopus.com/inward/record.url?scp=0032256634&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032256634&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0032256634

SN - 0163-1918

SP - 833

EP - 836

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

Y2 - 6 December 1998 through 9 December 1998

ER -

Interconnect design strategy: Structures, repeaters and materials toward 0.1 μm ULSIs with a Giga-hertz clock operation

Abstract

ASJC Scopus subject areas

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