In this paper, we propose a novel methodology for scheming interconnect strategy, such as what interconnect structure should be taken, how repeaters should be inserted, and when new met al. or dielectric materials should be adopted. In the methodology, the strategic system performance analysis model is newly developed as a calculation model that predicts LSI operation frequency and chip size with electrical parameters of transistors and interconnects as well as circuit configuration. The analysis with the model indicates that interconnect delay overcomes circuit block cycle time at a specific length; Dc_cross. Here tentatively, interconnects shorter than Dc Cro55 are called as local interconnects, and interconnects longer than that as global ones. The cross-sectional structures for local and global tiers are optimized separately. We also calculate global interconnect pitch and the chip size enlarged by the global interconnect pitch and the inserted repeaters, and then estimate the effectiveness of introducing new materials for interconnects and dielectrics.
- Delay modeling
- Interconnect structure
- Repeater insertion
- Signal delay
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering