Interconnection Allocation between Functional Units and Registers in High-Level Synthesis

Cong Hao, Jianmo Ni, Nan Wang, Takeshi Yoshimura

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

Data path interconnection on VLSI chips usually consumes a significant amount of both power and area. In this paper, we focus on the port assignment problem for binary commutative operators for interconnection complexity reduction. First, the port assignment problem is formulated on a constraint graph, and a practical method is proposed to find a valid and initial solution. For solution optimization, an elementary spanning-tree-transformation-based local search algorithm is proposed. To improve the efficiency of optimization, a matrix formulation, which meets the simplex tabuleau format, is proposed and thus the simplex method is adopted for optimization. Moreover, operation pivoting and successive pivoting are discussed for algorithm speedup. The experimental results show that on the randomly generated test cases, the matrix-based algorithm shows the highest solution optimality and is five times faster than the elementary transformation method. On the real high-level synthesis benchmarks, the matrix-based method reduced 14% interconnections, while the previous greedy algorithm reduced 8% on average.

Original languageEnglish
Pages (from-to)1140-1153
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume25
Issue number3
DOIs
Publication statusPublished - 2017 Mar 1

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Keywords

  • Graphical methodology
  • high-level synthesis (HLS)
  • interconnection
  • simplex method

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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