Abstract
This paper proposes a high-performance intra prediction architecture that can support H.264/AVC high profile. The proposed MB/block co-reordering can avoid data dependency and improve pipeline utilization. Therefore, the timing constraint of real-time 4kx2k encoding can be achieved with negligible quality loss. 16×16 prediction engine and 8×8 prediction engine work parallel for prediction and coefficients generating. A reordering interlaced reconstruction is also designed for fully pipelined architecture. It takes only 160 cycles to process one macroblock (MB). Hardware utilization of prediction and reconstruction modules is almost 100%. Furthermore, PE-reusable 8×8 intra predictor and hybrid SAD & SATD mode decision are proposed to save hardware cost. The design is implemented by 90nm CMOS technology with 113.2k gates and can encode 4kx2k video sequences at 60 fps with operation frequency of 310MHz.
| Original language | English |
|---|---|
| Title of host publication | 28th Picture Coding Symposium, PCS 2010 |
| Pages | 450-453 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2010 |
| Event | 28th Picture Coding Symposium, PCS 2010 - Nagoya Duration: 2010 Dec 8 → 2010 Dec 10 |
Other
| Other | 28th Picture Coding Symposium, PCS 2010 |
|---|---|
| City | Nagoya |
| Period | 10/12/8 → 10/12/10 |
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Keywords
- Fukuoka
- H.264/AVC
- Hardware architecture 2-7 Hibikino
- Intra prediction
- Japan
- Kitakyushu
- Wakamatsu-ku
ASJC Scopus subject areas
- Computer Graphics and Computer-Aided Design
- Computer Vision and Pattern Recognition
Cite this
Intra prediction architecture for H.264/AVC QFHD encoder. / He, Gang; Zhou, Dajiang; Zhou, Jinjia; Goto, Satoshi.
28th Picture Coding Symposium, PCS 2010. 2010. p. 450-453 5702533.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Intra prediction architecture for H.264/AVC QFHD encoder
AU - He, Gang
AU - Zhou, Dajiang
AU - Zhou, Jinjia
AU - Goto, Satoshi
PY - 2010
Y1 - 2010
N2 - This paper proposes a high-performance intra prediction architecture that can support H.264/AVC high profile. The proposed MB/block co-reordering can avoid data dependency and improve pipeline utilization. Therefore, the timing constraint of real-time 4kx2k encoding can be achieved with negligible quality loss. 16×16 prediction engine and 8×8 prediction engine work parallel for prediction and coefficients generating. A reordering interlaced reconstruction is also designed for fully pipelined architecture. It takes only 160 cycles to process one macroblock (MB). Hardware utilization of prediction and reconstruction modules is almost 100%. Furthermore, PE-reusable 8×8 intra predictor and hybrid SAD & SATD mode decision are proposed to save hardware cost. The design is implemented by 90nm CMOS technology with 113.2k gates and can encode 4kx2k video sequences at 60 fps with operation frequency of 310MHz.
AB - This paper proposes a high-performance intra prediction architecture that can support H.264/AVC high profile. The proposed MB/block co-reordering can avoid data dependency and improve pipeline utilization. Therefore, the timing constraint of real-time 4kx2k encoding can be achieved with negligible quality loss. 16×16 prediction engine and 8×8 prediction engine work parallel for prediction and coefficients generating. A reordering interlaced reconstruction is also designed for fully pipelined architecture. It takes only 160 cycles to process one macroblock (MB). Hardware utilization of prediction and reconstruction modules is almost 100%. Furthermore, PE-reusable 8×8 intra predictor and hybrid SAD & SATD mode decision are proposed to save hardware cost. The design is implemented by 90nm CMOS technology with 113.2k gates and can encode 4kx2k video sequences at 60 fps with operation frequency of 310MHz.
KW - Fukuoka
KW - H.264/AVC
KW - Hardware architecture 2-7 Hibikino
KW - Intra prediction
KW - Japan
KW - Kitakyushu
KW - Wakamatsu-ku
UR - http://www.scopus.com/inward/record.url?scp=79951789952&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79951789952&partnerID=8YFLogxK
U2 - 10.1109/PCS.2010.5702533
DO - 10.1109/PCS.2010.5702533
M3 - Conference contribution
AN - SCOPUS:79951789952
SN - 9781424471348
SP - 450
EP - 453
BT - 28th Picture Coding Symposium, PCS 2010
ER -