### Abstract

Three-dimensional integrated circuits (3-D ICs), i.e., stacked dies, can alleviate the interconnect problem coming with the decreasing feature size and increasing integration density, and promise a solution to heterogenous integration. The vertical connection, which is generally implemented by the through-the-silicon via, is a key technology for 3-D ICs. In this paper, given 3-D circuit placement or floorplan results with white space reserved between blocks for inter-layer interconnections, we proposed methods for assigning inter-layer signal via locations. Introducing a grid structure on the chip, the inter-layer via assignment of twolayer chips can be optimally solved by a convex-cost max-flow formulation with signal via congestion optimized. As for 3-D ICs with three or more layers, the inter-layer signal via assignment is modeled as an integral mincost multi-commodity flow problem, which is solved by a heuristic method based on the lagrangian relaxation. Relaxing the capacity constraints in the grids, we transfer the min-cost multi-commodity flow problem to a sequence of lagrangian sub-problems, which are solved by finding a sequence of shortest paths. The complexity of solving a lagrangian sub-problem is O(n_{nt}n^{2}
_{g}), where n_{nt} is the number of nets and n_{g} is the number of grids on one chip layer. The experimental results demonstrated the effectiveness of the method.

Original language | English |
---|---|

Pages (from-to) | 1080-1087 |

Number of pages | 8 |

Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |

Volume | E92-A |

Issue number | 4 |

DOIs | |

Publication status | Published - 2009 |

### Fingerprint

### Keywords

- Three dimensional integrated circuits
- Through-the-silicon via
- Via assignment

### ASJC Scopus subject areas

- Electrical and Electronic Engineering
- Computer Graphics and Computer-Aided Design
- Applied Mathematics
- Signal Processing

### Cite this

*IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences*,

*E92-A*(4), 1080-1087. https://doi.org/10.1587/transfun.E92.A.1080

**Lagrangian relaxation based inter-layer signal via assignment for 3-D ICs.** / Chen, Song; Ge, Liangwei; Chiang, Mei Fang; Yoshimura, Takeshi.

Research output: Contribution to journal › Article

*IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences*, vol. E92-A, no. 4, pp. 1080-1087. https://doi.org/10.1587/transfun.E92.A.1080

}

TY - JOUR

T1 - Lagrangian relaxation based inter-layer signal via assignment for 3-D ICs

AU - Chen, Song

AU - Ge, Liangwei

AU - Chiang, Mei Fang

AU - Yoshimura, Takeshi

PY - 2009

Y1 - 2009

N2 - Three-dimensional integrated circuits (3-D ICs), i.e., stacked dies, can alleviate the interconnect problem coming with the decreasing feature size and increasing integration density, and promise a solution to heterogenous integration. The vertical connection, which is generally implemented by the through-the-silicon via, is a key technology for 3-D ICs. In this paper, given 3-D circuit placement or floorplan results with white space reserved between blocks for inter-layer interconnections, we proposed methods for assigning inter-layer signal via locations. Introducing a grid structure on the chip, the inter-layer via assignment of twolayer chips can be optimally solved by a convex-cost max-flow formulation with signal via congestion optimized. As for 3-D ICs with three or more layers, the inter-layer signal via assignment is modeled as an integral mincost multi-commodity flow problem, which is solved by a heuristic method based on the lagrangian relaxation. Relaxing the capacity constraints in the grids, we transfer the min-cost multi-commodity flow problem to a sequence of lagrangian sub-problems, which are solved by finding a sequence of shortest paths. The complexity of solving a lagrangian sub-problem is O(nntn2 g), where nnt is the number of nets and ng is the number of grids on one chip layer. The experimental results demonstrated the effectiveness of the method.

AB - Three-dimensional integrated circuits (3-D ICs), i.e., stacked dies, can alleviate the interconnect problem coming with the decreasing feature size and increasing integration density, and promise a solution to heterogenous integration. The vertical connection, which is generally implemented by the through-the-silicon via, is a key technology for 3-D ICs. In this paper, given 3-D circuit placement or floorplan results with white space reserved between blocks for inter-layer interconnections, we proposed methods for assigning inter-layer signal via locations. Introducing a grid structure on the chip, the inter-layer via assignment of twolayer chips can be optimally solved by a convex-cost max-flow formulation with signal via congestion optimized. As for 3-D ICs with three or more layers, the inter-layer signal via assignment is modeled as an integral mincost multi-commodity flow problem, which is solved by a heuristic method based on the lagrangian relaxation. Relaxing the capacity constraints in the grids, we transfer the min-cost multi-commodity flow problem to a sequence of lagrangian sub-problems, which are solved by finding a sequence of shortest paths. The complexity of solving a lagrangian sub-problem is O(nntn2 g), where nnt is the number of nets and ng is the number of grids on one chip layer. The experimental results demonstrated the effectiveness of the method.

KW - Three dimensional integrated circuits

KW - Through-the-silicon via

KW - Via assignment

UR - http://www.scopus.com/inward/record.url?scp=77956052054&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77956052054&partnerID=8YFLogxK

U2 - 10.1587/transfun.E92.A.1080

DO - 10.1587/transfun.E92.A.1080

M3 - Article

AN - SCOPUS:77956052054

VL - E92-A

SP - 1080

EP - 1087

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 4

ER -