Lagrangian relaxation based pin assignment and Through-Silicon Via planning for 3-D SoCs

Wei Zhong, Song Chen, Yang Geng, Takeshi Yoshimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As technology advances, 3-D stacking of silicon layers that promises a solution to significantly alleviate the interconnect problem faced by current System-on-Chips (SoCs). In 3-D SoCs, judicious assignment of the pin locations and related vertical Through-Silicon Vias (TSVs) can improve the routing area and interconnection delay by reducing wire length and wire congestion. In this paper, we propose a significant algorithm to locate pin and TSV positions simultaneously for the two-pin net list in 3-D SoCs. Given a floorplan result, we formulate the pin assignment and TSV planning problem as a min-cost multi-commodity flow model and solve it based on lagrangian relaxation. By relaxing the capacity constraints in pin and TSV locations, we transform the min-cost multi-commodity flow problem to several min-cost max-flow problems that can be solved independently. A heuristic algorithm is also proposed to improve the result of lagrangian relaxation to guarantee the feasible solution. Experimental results show the effectiveness of the proposed algorithm.

Original languageEnglish
Title of host publicationProceedings of International Conference on ASIC
PublisherIEEE Computer Society
ISBN (Print)9781467364157
DOIs
Publication statusPublished - 2013
Event2013 IEEE 10th International Conference on ASIC, ASICON 2013 - Shenzhen
Duration: 2013 Oct 282013 Oct 31

Other

Other2013 IEEE 10th International Conference on ASIC, ASICON 2013
CityShenzhen
Period13/10/2813/10/31

Fingerprint

Planning
Silicon
Wire
Costs
Heuristic algorithms
System-on-chip

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Zhong, W., Chen, S., Geng, Y., & Yoshimura, T. (2013). Lagrangian relaxation based pin assignment and Through-Silicon Via planning for 3-D SoCs. In Proceedings of International Conference on ASIC [6811934] IEEE Computer Society. https://doi.org/10.1109/ASICON.2013.6811934

Lagrangian relaxation based pin assignment and Through-Silicon Via planning for 3-D SoCs. / Zhong, Wei; Chen, Song; Geng, Yang; Yoshimura, Takeshi.

Proceedings of International Conference on ASIC. IEEE Computer Society, 2013. 6811934.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhong, W, Chen, S, Geng, Y & Yoshimura, T 2013, Lagrangian relaxation based pin assignment and Through-Silicon Via planning for 3-D SoCs. in Proceedings of International Conference on ASIC., 6811934, IEEE Computer Society, 2013 IEEE 10th International Conference on ASIC, ASICON 2013, Shenzhen, 13/10/28. https://doi.org/10.1109/ASICON.2013.6811934
Zhong W, Chen S, Geng Y, Yoshimura T. Lagrangian relaxation based pin assignment and Through-Silicon Via planning for 3-D SoCs. In Proceedings of International Conference on ASIC. IEEE Computer Society. 2013. 6811934 https://doi.org/10.1109/ASICON.2013.6811934
Zhong, Wei ; Chen, Song ; Geng, Yang ; Yoshimura, Takeshi. / Lagrangian relaxation based pin assignment and Through-Silicon Via planning for 3-D SoCs. Proceedings of International Conference on ASIC. IEEE Computer Society, 2013.
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