Lagrangian relaxation based register placement for high-performance circuits

Mei Fang Chiang, Takumi Okamoto, Takeshi Yoshimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

To achieve low-skew clock distribution, clock tree synthesis (CTS) for local clock optimization is used so far. Challenged by the increasing design complexity and performance demand, a new strategy for local clock optimization is used along with register placement for high-performance circuits. Special local clock distribution is used and registers are legalized to fit required skew. In this paper, we study the register placement problem and formulate it as a minimum weighted maximum independent set problem on a weighted conflict graph. Then, we propose a novel Lagrangian relaxation based algorithm. By relaxing the overlap conflict constraints, the problem is transformed into a minimum weighted bipartite matching problem. Experiments show that our method can efficiently place all registers without overlaps with minimized total register movement.

Original languageEnglish
Title of host publicationProceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009
Pages511-516
Number of pages6
DOIs
Publication statusPublished - 2009
Event10th International Symposium on Quality Electronic Design, ISQED 2009 - San Jose, CA
Duration: 2009 Mar 162009 Mar 18

Other

Other10th International Symposium on Quality Electronic Design, ISQED 2009
CitySan Jose, CA
Period09/3/1609/3/18

Fingerprint

Clocks
Networks (circuits)
Experiments

Keywords

  • Clock skew
  • High-performance
  • Register

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Chiang, M. F., Okamoto, T., & Yoshimura, T. (2009). Lagrangian relaxation based register placement for high-performance circuits. In Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009 (pp. 511-516). [4810347] https://doi.org/10.1109/ISQED.2009.4810347

Lagrangian relaxation based register placement for high-performance circuits. / Chiang, Mei Fang; Okamoto, Takumi; Yoshimura, Takeshi.

Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009. 2009. p. 511-516 4810347.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chiang, MF, Okamoto, T & Yoshimura, T 2009, Lagrangian relaxation based register placement for high-performance circuits. in Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009., 4810347, pp. 511-516, 10th International Symposium on Quality Electronic Design, ISQED 2009, San Jose, CA, 09/3/16. https://doi.org/10.1109/ISQED.2009.4810347
Chiang MF, Okamoto T, Yoshimura T. Lagrangian relaxation based register placement for high-performance circuits. In Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009. 2009. p. 511-516. 4810347 https://doi.org/10.1109/ISQED.2009.4810347
Chiang, Mei Fang ; Okamoto, Takumi ; Yoshimura, Takeshi. / Lagrangian relaxation based register placement for high-performance circuits. Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009. 2009. pp. 511-516
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