Large within-die gate delay variations in sub-threshold logic circuits at low temperature

Ryo Takahashi, Hidehiro Takata, Tadashi Yasufuku, Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

Temperature dependence of 256 within-die random gate delay variations in sub-threshold logic circuits is measured in 40-nm CMOS test chips. When the temperature is reduced from 25\hboxC to-40\hboxC the sigma/average σμ of the gate delay at 0.3 V increases by 1.4 times. A newly developed model shows that σμ of the gate delay is proportional to 1/T for the first time, where T is the absolute temperature.

Original languageEnglish
Article number6392909
Pages (from-to)918-921
Number of pages4
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume59
Issue number12
DOIs
Publication statusPublished - 2012 Dec 1
Externally publishedYes

Keywords

  • Delay variations
  • device matrix array (DMA)
  • sub-threshold
  • temperature

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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