Temperature dependence of 256 within-die random gate delay variations in sub-threshold logic circuits is measured in 40-nm CMOS test chips. When the temperature is reduced from 25\hboxC to-40\hboxC the sigma/average σμ of the gate delay at 0.3 V increases by 1.4 times. A newly developed model shows that σμ of the gate delay is proportional to 1/T for the first time, where T is the absolute temperature.
|Number of pages||4|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2012 Dec 1|
- Delay variations
- device matrix array (DMA)
ASJC Scopus subject areas
- Electrical and Electronic Engineering