Large within-die gate delay variations in sub-threshold logic circuits at low temperature

Ryo Takahashi, Hidehiro Takata, Tadashi Yasufuku, Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

Temperature dependence of 256 within-die random gate delay variations in sub-threshold logic circuits is measured in 40-nm CMOS test chips. When the temperature is reduced from 25\hboxC to-40\hboxC the sigma/average σμ of the gate delay at 0.3 V increases by 1.4 times. A newly developed model shows that σμ of the gate delay is proportional to 1/T for the first time, where T is the absolute temperature.

Original languageEnglish
Article number6392909
Pages (from-to)918-921
Number of pages4
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume59
Issue number12
DOIs
Publication statusPublished - 2012
Externally publishedYes

Fingerprint

Threshold logic
Logic circuits
Temperature

Keywords

  • Delay variations
  • device matrix array (DMA)
  • sub-threshold
  • temperature

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Takahashi, R., Takata, H., Yasufuku, T., Fuketa, H., Takamiya, M., Nomura, M., ... Sakurai, T. (2012). Large within-die gate delay variations in sub-threshold logic circuits at low temperature. IEEE Transactions on Circuits and Systems II: Express Briefs, 59(12), 918-921. [6392909]. https://doi.org/10.1109/TCSII.2012.2231038

Large within-die gate delay variations in sub-threshold logic circuits at low temperature. / Takahashi, Ryo; Takata, Hidehiro; Yasufuku, Tadashi; Fuketa, Hiroshi; Takamiya, Makoto; Nomura, Masahiro; Shinohara, Hirofumi; Sakurai, Takayasu.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 59, No. 12, 6392909, 2012, p. 918-921.

Research output: Contribution to journalArticle

Takahashi, Ryo ; Takata, Hidehiro ; Yasufuku, Tadashi ; Fuketa, Hiroshi ; Takamiya, Makoto ; Nomura, Masahiro ; Shinohara, Hirofumi ; Sakurai, Takayasu. / Large within-die gate delay variations in sub-threshold logic circuits at low temperature. In: IEEE Transactions on Circuits and Systems II: Express Briefs. 2012 ; Vol. 59, No. 12. pp. 918-921.
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