Large within-die gate delay variations in sub-threshold logic circuits at low temperature

Ryo Takahashi; Hidehiro Takata; Tadashi Yasufuku; Hiroshi Fuketa; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai

doi:10.1109/TCSII.2012.2231038

Large within-die gate delay variations in sub-threshold logic circuits at low temperature

Ryo Takahashi^*, Hidehiro Takata, Tadashi Yasufuku, Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

9 Citations (Scopus)

Abstract

Temperature dependence of 256 within-die random gate delay variations in sub-threshold logic circuits is measured in 40-nm CMOS test chips. When the temperature is reduced from 25\hboxC to-40\hboxC the sigma/average σμ of the gate delay at 0.3 V increases by 1.4 times. A newly developed model shows that σμ of the gate delay is proportional to 1/T for the first time, where T is the absolute temperature.

Original language	English
Article number	6392909
Pages (from-to)	918-921
Number of pages	4
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	59
Issue number	12
DOIs	https://doi.org/10.1109/TCSII.2012.2231038
Publication status	Published - 2012
Externally published	Yes

Keywords

Delay variations
device matrix array (DMA)
sub-threshold
temperature

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/TCSII.2012.2231038

Cite this

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title = "Large within-die gate delay variations in sub-threshold logic circuits at low temperature",

abstract = "Temperature dependence of 256 within-die random gate delay variations in sub-threshold logic circuits is measured in 40-nm CMOS test chips. When the temperature is reduced from 25\hboxC to-40\hboxC the sigma/average σμ of the gate delay at 0.3 V increases by 1.4 times. A newly developed model shows that σμ of the gate delay is proportional to 1/T for the first time, where T is the absolute temperature.",

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doi = "10.1109/TCSII.2012.2231038",

language = "English",

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pages = "918--921",

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T1 - Large within-die gate delay variations in sub-threshold logic circuits at low temperature

AU - Takahashi, Ryo

AU - Takata, Hidehiro

AU - Yasufuku, Tadashi

AU - Fuketa, Hiroshi

AU - Takamiya, Makoto

AU - Nomura, Masahiro

AU - Shinohara, Hirofumi

AU - Sakurai, Takayasu

PY - 2012

Y1 - 2012

N2 - Temperature dependence of 256 within-die random gate delay variations in sub-threshold logic circuits is measured in 40-nm CMOS test chips. When the temperature is reduced from 25\hboxC to-40\hboxC the sigma/average σμ of the gate delay at 0.3 V increases by 1.4 times. A newly developed model shows that σμ of the gate delay is proportional to 1/T for the first time, where T is the absolute temperature.

AB - Temperature dependence of 256 within-die random gate delay variations in sub-threshold logic circuits is measured in 40-nm CMOS test chips. When the temperature is reduced from 25\hboxC to-40\hboxC the sigma/average σμ of the gate delay at 0.3 V increases by 1.4 times. A newly developed model shows that σμ of the gate delay is proportional to 1/T for the first time, where T is the absolute temperature.

KW - Delay variations

KW - device matrix array (DMA)

KW - sub-threshold

KW - temperature

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JO - IEEE Transactions on Circuits and Systems II: Express Briefs

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ER -

Large within-die gate delay variations in sub-threshold logic circuits at low temperature

Abstract

Keywords

ASJC Scopus subject areas

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