Layer assignment and equal-length routing for disordered pins in PCB Design

Ran Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

In recent printed circuit board (PCB) design, due to the high density of integration, the signal propagation delay or skew has become an important factor for a circuit performance. As the routing delay is proportional to the wire length, the controllability of the wire length is usually focused on. In this research, a heuristic algorithm to get equal-length routing for disordered pins in PCB design is proposed. The approach initially checks the longest common subsequence of source and target pin sets to assign layers for pins. Single commodity flow is then carried out to generate the base routes. Finally, considering target length requirement and available routing region, R-flip and C-flip are adopted to adjust the wire length. The experimental results show that the proposed method is able to obtain the routes with better wire length balance and smaller worst length error in reasonable CPU times.

Original languageEnglish
Pages (from-to)75-84
Number of pages10
JournalIPSJ Transactions on System LSI Design Methodology
Volume8
DOIs
Publication statusPublished - 2015 Feb 1

Fingerprint

Printed circuit boards
Wire
Heuristic algorithms
Controllability
Program processors
Networks (circuits)

Keywords

  • EDA
  • Equal-length routing
  • PCB routing
  • Single commodity flow

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

Layer assignment and equal-length routing for disordered pins in PCB Design. / Zhang, Ran; Pan, Tieyuan; Zhu, Li; Watanabe, Takahiro.

In: IPSJ Transactions on System LSI Design Methodology, Vol. 8, 01.02.2015, p. 75-84.

Research output: Contribution to journalArticle

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