Layout generator with flexible grid assignment for area efficient standard cell

Shinichi Nishizawa*, Tohru Ishihara, Hidetoshi Onodera

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


This paper discusses a standard cell layout generator that can be used to generate a standard cell library optimized to a target application. It can generate an area efficient layout from a virtual-grid symbolic layout with the ability of flexible grid positioning that considers local design rules enforced in a scaled technology. The generator reduces the cost of library design and enables an optimization of each cell with detailed layout information that can be used to estimate the performance of the cell under design. A standard cell library has been generated for commercial 28-nm FDSOI CMOS process using the proposed layout generator, and used for circuit design. Correct operation of designed circuit is observed form fabricated chip test.

Original languageEnglish
Pages (from-to)131-135
Number of pages5
JournalIPSJ Transactions on System LSI Design Methodology
Publication statusPublished - 2015 Feb 1
Externally publishedYes


  • Computer-Aided design
  • Layout generator
  • Standard cell library

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering


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