Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs

Kan Wang, Sheqin Dong, Yuchun Ma, Goto Satoshi, Jason Cong

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    3D IC has become an attractive technology as it decreases interconnection distance and improves performance. However, it is faced with heat dissipation and temperature problem seriously. The high temperature will increase the interconnection delay, and lead to degradation of performance. Through-silicon-via (TSV) has been shown as an effective way to optimize heat distribution. However, the distribution of TSVs will potentially influence the interconnection delay. In this paper, we propose a performance-driven 3D TSV-planning (3D-PTSP) algorithm, which can generate good TSV distribution, to improve temperature. The thermal effects on critical path delay are analyzed with leakage power-temperature-delay dependence considered. A priority based TSV redistribution algorithm and network flow based signal via allocation algorithm help to improve both TSV number and critical path delay without increasing temperature. Experimental results show that the proposed method can improve total via number by 8.9% and reduce critical path delay by 15.8%.

    Original languageEnglish
    Title of host publicationProceedings - International Symposium on Quality Electronic Design, ISQED
    Pages129-136
    Number of pages8
    DOIs
    Publication statusPublished - 2012
    Event13th International Symposium on Quality Electronic Design, ISQED 2012 - Santa Clara, CA
    Duration: 2012 Mar 192012 Mar 21

    Other

    Other13th International Symposium on Quality Electronic Design, ISQED 2012
    CitySanta Clara, CA
    Period12/3/1912/3/21

    Fingerprint

    Planning
    Silicon
    Temperature
    Heat losses
    Thermal effects
    Degradation

    Keywords

    • Critical path delay
    • Leakage power
    • Leakage power-temperature-delay dependence
    • Signal TSV allocation

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering
    • Safety, Risk, Reliability and Quality

    Cite this

    Wang, K., Dong, S., Ma, Y., Satoshi, G., & Cong, J. (2012). Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs. In Proceedings - International Symposium on Quality Electronic Design, ISQED (pp. 129-136). [6187485] https://doi.org/10.1109/ISQED.2012.6187485

    Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs. / Wang, Kan; Dong, Sheqin; Ma, Yuchun; Satoshi, Goto; Cong, Jason.

    Proceedings - International Symposium on Quality Electronic Design, ISQED. 2012. p. 129-136 6187485.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Wang, K, Dong, S, Ma, Y, Satoshi, G & Cong, J 2012, Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs. in Proceedings - International Symposium on Quality Electronic Design, ISQED., 6187485, pp. 129-136, 13th International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, 12/3/19. https://doi.org/10.1109/ISQED.2012.6187485
    Wang K, Dong S, Ma Y, Satoshi G, Cong J. Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs. In Proceedings - International Symposium on Quality Electronic Design, ISQED. 2012. p. 129-136. 6187485 https://doi.org/10.1109/ISQED.2012.6187485
    Wang, Kan ; Dong, Sheqin ; Ma, Yuchun ; Satoshi, Goto ; Cong, Jason. / Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs. Proceedings - International Symposium on Quality Electronic Design, ISQED. 2012. pp. 129-136
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