Leakage power aware scheduling in high-level synthesis

Nan Wang, Song Chen, Cong Hao, Haoran Zhang, Takeshi Yoshimura

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

In this paper, we address the problem of scheduling operations into control steps with a dual threshold voltage (dual-Vth) technique, under timing and resource constraints. We present a two-stage algorithm for leakage power optimization. In the threshold voltage (Vth) assignment stage, the proposed algorithm first initializes all the operations to high-V th, and then it iteratively shortens the critical path delay by reassigning the set of operations covering all the critical paths to low-V th until the timing constraint is met. In the scheduling stage, a modified force-directed scheduling is implemented to schedule operations and to adjust threshold voltage assignments with a consideration of the resource constraints. To eliminate the potential resource constraint violations, the operations' threshold voltage adjustment problem is formulated as a "weighted interval scheduling" problem. The experimental results show that our proposed method performs better in both running time and leakage power reduction compared with MWIS [3].

Original languageEnglish
Pages (from-to)940-951
Number of pages12
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE97-A
Issue number4
DOIs
Publication statusPublished - 2014

Fingerprint

High-level Synthesis
Threshold voltage
Leakage
Scheduling
Resource Constraints
Voltage
Critical Path
Timing
Assignment
Scheduling Problem
Adjustment
Schedule
Covering
Eliminate
High level synthesis
Interval
Optimization
Experimental Results

Keywords

  • Dual-Vth
  • Leakage power
  • Max-flow min-cut

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Graphics and Computer-Aided Design
  • Applied Mathematics
  • Signal Processing

Cite this

Leakage power aware scheduling in high-level synthesis. / Wang, Nan; Chen, Song; Hao, Cong; Zhang, Haoran; Yoshimura, Takeshi.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E97-A, No. 4, 2014, p. 940-951.

Research output: Contribution to journalArticle

Wang, Nan ; Chen, Song ; Hao, Cong ; Zhang, Haoran ; Yoshimura, Takeshi. / Leakage power aware scheduling in high-level synthesis. In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2014 ; Vol. E97-A, No. 4. pp. 940-951.
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