Leakage-Power-Aware Scheduling with Dual-Threshold Voltage Design

Nan Wang, Wei Zhong, Cong Hao, Song Chen, Takeshi Yoshimura, Yu Zhu

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

The exponential increase in leakage power and the substantial power-saving opportunities provided by scheduling have made dual-Threshold voltage (dual-Vth) an attractive choice for low-leakage-power designs. In this paper, we work under the assumption that functional units (FUs) are allocated after scheduling, and fully explore the solution space of scheduling with dual-Vth operations to optimize the leakage power of the FUs. First, a binding conflict graph (BCG)-based scheduling method is presented to minimize the number of FUs. Second, the BCG-based method is extended to allow scheduling with dual-Vth operation targeting the minimization of leakage power. In timing-constrained scheduling, each operation in the data flow is initialized with low-Vth. Then, starting from an operation schedule with the timing constraint satisfied, we scale the sets of low-Vth operations in the off-critical paths with high-Vth so as to reduce the number of low-Vth FUs without increasing the total delay. Finally, a scheduling method for minimizing the leakage power under both timing and resource constraints is presented. The results of benchmark tests show that the proposed algorithms can reduce the leakage power reported in previous works by 10.2% while maintaining high circuit performance.

Original languageEnglish
Article number7434043
Pages (from-to)3067-3079
Number of pages13
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume24
Issue number10
DOIs
Publication statusPublished - 2016 Oct 1

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Threshold voltage
Scheduling
Networks (circuits)

Keywords

  • Dual-Vth
  • functional unit
  • leakage-power optimization
  • scheduling.

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Leakage-Power-Aware Scheduling with Dual-Threshold Voltage Design. / Wang, Nan; Zhong, Wei; Hao, Cong; Chen, Song; Yoshimura, Takeshi; Zhu, Yu.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, No. 10, 7434043, 01.10.2016, p. 3067-3079.

Research output: Contribution to journalArticle

Wang, Nan ; Zhong, Wei ; Hao, Cong ; Chen, Song ; Yoshimura, Takeshi ; Zhu, Yu. / Leakage-Power-Aware Scheduling with Dual-Threshold Voltage Design. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2016 ; Vol. 24, No. 10. pp. 3067-3079.
@article{a419a6ccf8a9414e98f02665c6426ce0,
title = "Leakage-Power-Aware Scheduling with Dual-Threshold Voltage Design",
abstract = "The exponential increase in leakage power and the substantial power-saving opportunities provided by scheduling have made dual-Threshold voltage (dual-Vth) an attractive choice for low-leakage-power designs. In this paper, we work under the assumption that functional units (FUs) are allocated after scheduling, and fully explore the solution space of scheduling with dual-Vth operations to optimize the leakage power of the FUs. First, a binding conflict graph (BCG)-based scheduling method is presented to minimize the number of FUs. Second, the BCG-based method is extended to allow scheduling with dual-Vth operation targeting the minimization of leakage power. In timing-constrained scheduling, each operation in the data flow is initialized with low-Vth. Then, starting from an operation schedule with the timing constraint satisfied, we scale the sets of low-Vth operations in the off-critical paths with high-Vth so as to reduce the number of low-Vth FUs without increasing the total delay. Finally, a scheduling method for minimizing the leakage power under both timing and resource constraints is presented. The results of benchmark tests show that the proposed algorithms can reduce the leakage power reported in previous works by 10.2{\%} while maintaining high circuit performance.",
keywords = "Dual-Vth, functional unit, leakage-power optimization, scheduling.",
author = "Nan Wang and Wei Zhong and Cong Hao and Song Chen and Takeshi Yoshimura and Yu Zhu",
year = "2016",
month = "10",
day = "1",
doi = "10.1109/TVLSI.2016.2535221",
language = "English",
volume = "24",
pages = "3067--3079",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "10",

}

TY - JOUR

T1 - Leakage-Power-Aware Scheduling with Dual-Threshold Voltage Design

AU - Wang, Nan

AU - Zhong, Wei

AU - Hao, Cong

AU - Chen, Song

AU - Yoshimura, Takeshi

AU - Zhu, Yu

PY - 2016/10/1

Y1 - 2016/10/1

N2 - The exponential increase in leakage power and the substantial power-saving opportunities provided by scheduling have made dual-Threshold voltage (dual-Vth) an attractive choice for low-leakage-power designs. In this paper, we work under the assumption that functional units (FUs) are allocated after scheduling, and fully explore the solution space of scheduling with dual-Vth operations to optimize the leakage power of the FUs. First, a binding conflict graph (BCG)-based scheduling method is presented to minimize the number of FUs. Second, the BCG-based method is extended to allow scheduling with dual-Vth operation targeting the minimization of leakage power. In timing-constrained scheduling, each operation in the data flow is initialized with low-Vth. Then, starting from an operation schedule with the timing constraint satisfied, we scale the sets of low-Vth operations in the off-critical paths with high-Vth so as to reduce the number of low-Vth FUs without increasing the total delay. Finally, a scheduling method for minimizing the leakage power under both timing and resource constraints is presented. The results of benchmark tests show that the proposed algorithms can reduce the leakage power reported in previous works by 10.2% while maintaining high circuit performance.

AB - The exponential increase in leakage power and the substantial power-saving opportunities provided by scheduling have made dual-Threshold voltage (dual-Vth) an attractive choice for low-leakage-power designs. In this paper, we work under the assumption that functional units (FUs) are allocated after scheduling, and fully explore the solution space of scheduling with dual-Vth operations to optimize the leakage power of the FUs. First, a binding conflict graph (BCG)-based scheduling method is presented to minimize the number of FUs. Second, the BCG-based method is extended to allow scheduling with dual-Vth operation targeting the minimization of leakage power. In timing-constrained scheduling, each operation in the data flow is initialized with low-Vth. Then, starting from an operation schedule with the timing constraint satisfied, we scale the sets of low-Vth operations in the off-critical paths with high-Vth so as to reduce the number of low-Vth FUs without increasing the total delay. Finally, a scheduling method for minimizing the leakage power under both timing and resource constraints is presented. The results of benchmark tests show that the proposed algorithms can reduce the leakage power reported in previous works by 10.2% while maintaining high circuit performance.

KW - Dual-Vth

KW - functional unit

KW - leakage-power optimization

KW - scheduling.

UR - http://www.scopus.com/inward/record.url?scp=84960981607&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84960981607&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2016.2535221

DO - 10.1109/TVLSI.2016.2535221

M3 - Article

VL - 24

SP - 3067

EP - 3079

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 10

M1 - 7434043

ER -