Live demonstration: FPGA based 3840×2160 video decoding and displaying system

Haoming Zhang, Dajiang Zhou, Satoshi Goto

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    A demonstration of FPGA-based 3840×2160 UHDTV (Ultra-high definition TV) H.264 video decoding and displaying system is proposed in this paper. The proposed system can decode and display 3840×2160 video by two Altera Stratix III DE3 FPGA boards, which are connected together with each other by HSTC cable. Video processing system requires high memory bandwidth. This paper locate decoder module and display module in different FPGA board and try to use two off-chip memory of the two boards, in order to provide more memory bandwidth.

    Original languageEnglish
    Title of host publicationIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages169-170
    Number of pages2
    Volume2015-February
    EditionFebruary
    DOIs
    Publication statusPublished - 2015 Feb 5
    Event2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 - Ishigaki Island, Okinawa, Japan
    Duration: 2014 Nov 172014 Nov 20

    Other

    Other2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
    CountryJapan
    CityIshigaki Island, Okinawa
    Period14/11/1714/11/20

    Keywords

    • FPGA
    • H.264
    • UHDTV
    • Video Decoder

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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  • Cite this

    Zhang, H., Zhou, D., & Goto, S. (2015). Live demonstration: FPGA based 3840×2160 video decoding and displaying system. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS (February ed., Vol. 2015-February, pp. 169-170). [7032745] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2014.7032745