Abstract
A demonstration of FPGA-based 3840×2160 UHDTV (Ultra-high definition TV) H.264 video decoding and displaying system is proposed in this paper. The proposed system can decode and display 3840×2160 video by two Altera Stratix III DE3 FPGA boards, which are connected together with each other by HSTC cable. Video processing system requires high memory bandwidth. This paper locate decoder module and display module in different FPGA board and try to use two off-chip memory of the two boards, in order to provide more memory bandwidth.
Original language | English |
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Title of host publication | IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 169-170 |
Number of pages | 2 |
Volume | 2015-February |
Edition | February |
DOIs | |
Publication status | Published - 2015 Feb 5 |
Event | 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 - Ishigaki Island, Okinawa, Japan Duration: 2014 Nov 17 → 2014 Nov 20 |
Other
Other | 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 |
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Country/Territory | Japan |
City | Ishigaki Island, Okinawa |
Period | 14/11/17 → 14/11/20 |
Keywords
- FPGA
- H.264
- UHDTV
- Video Decoder
ASJC Scopus subject areas
- Electrical and Electronic Engineering