Look up table compaction based on folding of logic functions

Shinji Kimura, Atsushi Ishii, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara, Katsumasa Watanabe

Research output: Contribution to journalArticle

Abstract

The paper describes the folding method of logic functions to reduce the size of memories to keep the functions. The folding is based on the relation of fractions of logic functions. If the logic function includes 2 or 3 same parts, then only one part should be kept and other parts can be omitted. We show that the logic function of 1-bit addition can be reduced to half size using the bit-wise NOT relation and the bit-wise OR relation. The paper also introduces 3-1 LUT's with the folding mechanism. A full adder can be implemented using only one 3-1 LUT with the folding. Multi-bit AND and OR operations can be mapped to our LUT's not using the extra cascading circuit but using the carry circuit for addition. We have also tested the mapping capability of 4 input functions to our 3-1 LUT's with folding and carry propagation mechanisms. We have shown the reduction of the area consumption when using our LUT's compared to the case using 4-1 LUT's on several benchmark circuits.

Original languageEnglish
Pages (from-to)2701-2707
Number of pages7
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE85-A
Issue number12
Publication statusPublished - 2002 Dec

Fingerprint

Compaction
Look-up Table
Folding
Logic
Adders
Networks (circuits)
Propagation
Benchmark
Data storage equipment

Keywords

  • Field programmable gate array (FPGA)
  • LUT architecture
  • Reconfigurable logic

ASJC Scopus subject areas

  • Hardware and Architecture
  • Information Systems
  • Electrical and Electronic Engineering

Cite this

Kimura, S., Ishii, A., Horiyama, T., Nakanishi, M., Kajihara, H., & Watanabe, K. (2002). Look up table compaction based on folding of logic functions. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E85-A(12), 2701-2707.

Look up table compaction based on folding of logic functions. / Kimura, Shinji; Ishii, Atsushi; Horiyama, Takashi; Nakanishi, Masaki; Kajihara, Hirotsugu; Watanabe, Katsumasa.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E85-A, No. 12, 12.2002, p. 2701-2707.

Research output: Contribution to journalArticle

Kimura, S, Ishii, A, Horiyama, T, Nakanishi, M, Kajihara, H & Watanabe, K 2002, 'Look up table compaction based on folding of logic functions', IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E85-A, no. 12, pp. 2701-2707.
Kimura, Shinji ; Ishii, Atsushi ; Horiyama, Takashi ; Nakanishi, Masaki ; Kajihara, Hirotsugu ; Watanabe, Katsumasa. / Look up table compaction based on folding of logic functions. In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2002 ; Vol. E85-A, No. 12. pp. 2701-2707.
@article{afba63da197b4ec699d8be3bab302a24,
title = "Look up table compaction based on folding of logic functions",
abstract = "The paper describes the folding method of logic functions to reduce the size of memories to keep the functions. The folding is based on the relation of fractions of logic functions. If the logic function includes 2 or 3 same parts, then only one part should be kept and other parts can be omitted. We show that the logic function of 1-bit addition can be reduced to half size using the bit-wise NOT relation and the bit-wise OR relation. The paper also introduces 3-1 LUT's with the folding mechanism. A full adder can be implemented using only one 3-1 LUT with the folding. Multi-bit AND and OR operations can be mapped to our LUT's not using the extra cascading circuit but using the carry circuit for addition. We have also tested the mapping capability of 4 input functions to our 3-1 LUT's with folding and carry propagation mechanisms. We have shown the reduction of the area consumption when using our LUT's compared to the case using 4-1 LUT's on several benchmark circuits.",
keywords = "Field programmable gate array (FPGA), LUT architecture, Reconfigurable logic",
author = "Shinji Kimura and Atsushi Ishii and Takashi Horiyama and Masaki Nakanishi and Hirotsugu Kajihara and Katsumasa Watanabe",
year = "2002",
month = "12",
language = "English",
volume = "E85-A",
pages = "2701--2707",
journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
issn = "0916-8508",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "12",

}

TY - JOUR

T1 - Look up table compaction based on folding of logic functions

AU - Kimura, Shinji

AU - Ishii, Atsushi

AU - Horiyama, Takashi

AU - Nakanishi, Masaki

AU - Kajihara, Hirotsugu

AU - Watanabe, Katsumasa

PY - 2002/12

Y1 - 2002/12

N2 - The paper describes the folding method of logic functions to reduce the size of memories to keep the functions. The folding is based on the relation of fractions of logic functions. If the logic function includes 2 or 3 same parts, then only one part should be kept and other parts can be omitted. We show that the logic function of 1-bit addition can be reduced to half size using the bit-wise NOT relation and the bit-wise OR relation. The paper also introduces 3-1 LUT's with the folding mechanism. A full adder can be implemented using only one 3-1 LUT with the folding. Multi-bit AND and OR operations can be mapped to our LUT's not using the extra cascading circuit but using the carry circuit for addition. We have also tested the mapping capability of 4 input functions to our 3-1 LUT's with folding and carry propagation mechanisms. We have shown the reduction of the area consumption when using our LUT's compared to the case using 4-1 LUT's on several benchmark circuits.

AB - The paper describes the folding method of logic functions to reduce the size of memories to keep the functions. The folding is based on the relation of fractions of logic functions. If the logic function includes 2 or 3 same parts, then only one part should be kept and other parts can be omitted. We show that the logic function of 1-bit addition can be reduced to half size using the bit-wise NOT relation and the bit-wise OR relation. The paper also introduces 3-1 LUT's with the folding mechanism. A full adder can be implemented using only one 3-1 LUT with the folding. Multi-bit AND and OR operations can be mapped to our LUT's not using the extra cascading circuit but using the carry circuit for addition. We have also tested the mapping capability of 4 input functions to our 3-1 LUT's with folding and carry propagation mechanisms. We have shown the reduction of the area consumption when using our LUT's compared to the case using 4-1 LUT's on several benchmark circuits.

KW - Field programmable gate array (FPGA)

KW - LUT architecture

KW - Reconfigurable logic

UR - http://www.scopus.com/inward/record.url?scp=0036999599&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036999599&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0036999599

VL - E85-A

SP - 2701

EP - 2707

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 12

ER -