Approximate computing is applicable to improve hardware performance by sacrificing some accuracy for error-Tolerant applications, where multiplication is a key arithmetic operation. In this paper, we propose a low-cost approximate multiplier design by employing new probability-driven inexact 4:2, 6:2, 8:2 compressors and inexact half-Adders. This compressor design is explored to reduce the height of partial product matrix into two rows. Different levels of accuracy can be achieved through a grouped error recovery scheme that employs different numbers of error compensation vectors for error reduction. The mean relative error distance (MRED) of the proposed multiplier design is from 1.07% to 7.86%. Compared with the Wallace multiplier using SMIC 40nm process, the most accurate variant of the proposed design reduces power by 50.52%, area by 52.46%, and delay by 33.90%. The proposed multiplier design has a better accuracy-performance trade-off than other designs. Moreover, the efficiency of approximate multipliers is assessed in an image processing application.