Abstract
Approximate computing is applicable to improve hardware performance by sacrificing some accuracy for error-Tolerant applications, where multiplication is a key arithmetic operation. In this paper, we propose a low-cost approximate multiplier design by employing new probability-driven inexact 4:2, 6:2, 8:2 compressors and inexact half-Adders. This compressor design is explored to reduce the height of partial product matrix into two rows. Different levels of accuracy can be achieved through a grouped error recovery scheme that employs different numbers of error compensation vectors for error reduction. The mean relative error distance (MRED) of the proposed multiplier design is from 1.07% to 7.86%. Compared with the Wallace multiplier using SMIC 40nm process, the most accurate variant of the proposed design reduces power by 50.52%, area by 52.46%, and delay by 33.90%. The proposed multiplier design has a better accuracy-performance trade-off than other designs. Moreover, the efficiency of approximate multipliers is assessed in an image processing application.
| Original language | English |
|---|---|
| Title of host publication | 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 291-294 |
| Number of pages | 4 |
| ISBN (Electronic) | 9781538682401 |
| DOIs | |
| Publication status | Published - 2019 Jan 8 |
| Event | 14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018 - Chengdu, China Duration: 2018 Oct 26 → 2018 Oct 30 |
Publication series
| Name | 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018 |
|---|
Conference
| Conference | 14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018 |
|---|---|
| Country | China |
| City | Chengdu |
| Period | 18/10/26 → 18/10/30 |
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Keywords
- Approximate computing
- Error recovery
- Inexact compressor
- Multiplier
ASJC Scopus subject areas
- Biomedical Engineering
- Electrical and Electronic Engineering
- Instrumentation
Cite this
Low-Cost Approximate Multiplier Design using Probability-Driven Inexact Compressors. / Guo, Yi; Sun, Heming; Guo, Li; Kimura, Shinji.
2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 291-294 8605570 (2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Low-Cost Approximate Multiplier Design using Probability-Driven Inexact Compressors
AU - Guo, Yi
AU - Sun, Heming
AU - Guo, Li
AU - Kimura, Shinji
PY - 2019/1/8
Y1 - 2019/1/8
N2 - Approximate computing is applicable to improve hardware performance by sacrificing some accuracy for error-Tolerant applications, where multiplication is a key arithmetic operation. In this paper, we propose a low-cost approximate multiplier design by employing new probability-driven inexact 4:2, 6:2, 8:2 compressors and inexact half-Adders. This compressor design is explored to reduce the height of partial product matrix into two rows. Different levels of accuracy can be achieved through a grouped error recovery scheme that employs different numbers of error compensation vectors for error reduction. The mean relative error distance (MRED) of the proposed multiplier design is from 1.07% to 7.86%. Compared with the Wallace multiplier using SMIC 40nm process, the most accurate variant of the proposed design reduces power by 50.52%, area by 52.46%, and delay by 33.90%. The proposed multiplier design has a better accuracy-performance trade-off than other designs. Moreover, the efficiency of approximate multipliers is assessed in an image processing application.
AB - Approximate computing is applicable to improve hardware performance by sacrificing some accuracy for error-Tolerant applications, where multiplication is a key arithmetic operation. In this paper, we propose a low-cost approximate multiplier design by employing new probability-driven inexact 4:2, 6:2, 8:2 compressors and inexact half-Adders. This compressor design is explored to reduce the height of partial product matrix into two rows. Different levels of accuracy can be achieved through a grouped error recovery scheme that employs different numbers of error compensation vectors for error reduction. The mean relative error distance (MRED) of the proposed multiplier design is from 1.07% to 7.86%. Compared with the Wallace multiplier using SMIC 40nm process, the most accurate variant of the proposed design reduces power by 50.52%, area by 52.46%, and delay by 33.90%. The proposed multiplier design has a better accuracy-performance trade-off than other designs. Moreover, the efficiency of approximate multipliers is assessed in an image processing application.
KW - Approximate computing
KW - Error recovery
KW - Inexact compressor
KW - Multiplier
UR - http://www.scopus.com/inward/record.url?scp=85062208056&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85062208056&partnerID=8YFLogxK
U2 - 10.1109/APCCAS.2018.8605570
DO - 10.1109/APCCAS.2018.8605570
M3 - Conference contribution
AN - SCOPUS:85062208056
T3 - 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018
SP - 291
EP - 294
BT - 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018
PB - Institute of Electrical and Electronics Engineers Inc.
ER -