Low-Cost Approximate Multiplier Design using Probability-Driven Inexact Compressors

Yi Guo, Heming Sun, Li Guo, Shinji Kimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Approximate computing is applicable to improve hardware performance by sacrificing some accuracy for error-Tolerant applications, where multiplication is a key arithmetic operation. In this paper, we propose a low-cost approximate multiplier design by employing new probability-driven inexact 4:2, 6:2, 8:2 compressors and inexact half-Adders. This compressor design is explored to reduce the height of partial product matrix into two rows. Different levels of accuracy can be achieved through a grouped error recovery scheme that employs different numbers of error compensation vectors for error reduction. The mean relative error distance (MRED) of the proposed multiplier design is from 1.07% to 7.86%. Compared with the Wallace multiplier using SMIC 40nm process, the most accurate variant of the proposed design reduces power by 50.52%, area by 52.46%, and delay by 33.90%. The proposed multiplier design has a better accuracy-performance trade-off than other designs. Moreover, the efficiency of approximate multipliers is assessed in an image processing application.

Original languageEnglish
Title of host publication2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages291-294
Number of pages4
ISBN (Electronic)9781538682401
DOIs
Publication statusPublished - 2019 Jan 8
Event14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018 - Chengdu, China
Duration: 2018 Oct 262018 Oct 30

Publication series

Name2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018

Conference

Conference14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018
CountryChina
CityChengdu
Period18/10/2618/10/30

Fingerprint

multipliers
compressors
Compressors
Costs
Error compensation
Adders
multiplication
image processing
hardware
Image processing
recovery
Hardware
products
matrices

Keywords

  • Approximate computing
  • Error recovery
  • Inexact compressor
  • Multiplier

ASJC Scopus subject areas

  • Biomedical Engineering
  • Electrical and Electronic Engineering
  • Instrumentation

Cite this

Guo, Y., Sun, H., Guo, L., & Kimura, S. (2019). Low-Cost Approximate Multiplier Design using Probability-Driven Inexact Compressors. In 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018 (pp. 291-294). [8605570] (2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2018.8605570

Low-Cost Approximate Multiplier Design using Probability-Driven Inexact Compressors. / Guo, Yi; Sun, Heming; Guo, Li; Kimura, Shinji.

2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 291-294 8605570 (2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Guo, Y, Sun, H, Guo, L & Kimura, S 2019, Low-Cost Approximate Multiplier Design using Probability-Driven Inexact Compressors. in 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018., 8605570, 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Institute of Electrical and Electronics Engineers Inc., pp. 291-294, 14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Chengdu, China, 18/10/26. https://doi.org/10.1109/APCCAS.2018.8605570
Guo Y, Sun H, Guo L, Kimura S. Low-Cost Approximate Multiplier Design using Probability-Driven Inexact Compressors. In 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018. Institute of Electrical and Electronics Engineers Inc. 2019. p. 291-294. 8605570. (2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018). https://doi.org/10.1109/APCCAS.2018.8605570
Guo, Yi ; Sun, Heming ; Guo, Li ; Kimura, Shinji. / Low-Cost Approximate Multiplier Design using Probability-Driven Inexact Compressors. 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 291-294 (2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018).
@inproceedings{2d1fdf5d2dbc4b18a6fedf31e8f7ce03,
title = "Low-Cost Approximate Multiplier Design using Probability-Driven Inexact Compressors",
abstract = "Approximate computing is applicable to improve hardware performance by sacrificing some accuracy for error-Tolerant applications, where multiplication is a key arithmetic operation. In this paper, we propose a low-cost approximate multiplier design by employing new probability-driven inexact 4:2, 6:2, 8:2 compressors and inexact half-Adders. This compressor design is explored to reduce the height of partial product matrix into two rows. Different levels of accuracy can be achieved through a grouped error recovery scheme that employs different numbers of error compensation vectors for error reduction. The mean relative error distance (MRED) of the proposed multiplier design is from 1.07{\%} to 7.86{\%}. Compared with the Wallace multiplier using SMIC 40nm process, the most accurate variant of the proposed design reduces power by 50.52{\%}, area by 52.46{\%}, and delay by 33.90{\%}. The proposed multiplier design has a better accuracy-performance trade-off than other designs. Moreover, the efficiency of approximate multipliers is assessed in an image processing application.",
keywords = "Approximate computing, Error recovery, Inexact compressor, Multiplier",
author = "Yi Guo and Heming Sun and Li Guo and Shinji Kimura",
year = "2019",
month = "1",
day = "8",
doi = "10.1109/APCCAS.2018.8605570",
language = "English",
series = "2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "291--294",
booktitle = "2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018",

}

TY - GEN

T1 - Low-Cost Approximate Multiplier Design using Probability-Driven Inexact Compressors

AU - Guo, Yi

AU - Sun, Heming

AU - Guo, Li

AU - Kimura, Shinji

PY - 2019/1/8

Y1 - 2019/1/8

N2 - Approximate computing is applicable to improve hardware performance by sacrificing some accuracy for error-Tolerant applications, where multiplication is a key arithmetic operation. In this paper, we propose a low-cost approximate multiplier design by employing new probability-driven inexact 4:2, 6:2, 8:2 compressors and inexact half-Adders. This compressor design is explored to reduce the height of partial product matrix into two rows. Different levels of accuracy can be achieved through a grouped error recovery scheme that employs different numbers of error compensation vectors for error reduction. The mean relative error distance (MRED) of the proposed multiplier design is from 1.07% to 7.86%. Compared with the Wallace multiplier using SMIC 40nm process, the most accurate variant of the proposed design reduces power by 50.52%, area by 52.46%, and delay by 33.90%. The proposed multiplier design has a better accuracy-performance trade-off than other designs. Moreover, the efficiency of approximate multipliers is assessed in an image processing application.

AB - Approximate computing is applicable to improve hardware performance by sacrificing some accuracy for error-Tolerant applications, where multiplication is a key arithmetic operation. In this paper, we propose a low-cost approximate multiplier design by employing new probability-driven inexact 4:2, 6:2, 8:2 compressors and inexact half-Adders. This compressor design is explored to reduce the height of partial product matrix into two rows. Different levels of accuracy can be achieved through a grouped error recovery scheme that employs different numbers of error compensation vectors for error reduction. The mean relative error distance (MRED) of the proposed multiplier design is from 1.07% to 7.86%. Compared with the Wallace multiplier using SMIC 40nm process, the most accurate variant of the proposed design reduces power by 50.52%, area by 52.46%, and delay by 33.90%. The proposed multiplier design has a better accuracy-performance trade-off than other designs. Moreover, the efficiency of approximate multipliers is assessed in an image processing application.

KW - Approximate computing

KW - Error recovery

KW - Inexact compressor

KW - Multiplier

UR - http://www.scopus.com/inward/record.url?scp=85062208056&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85062208056&partnerID=8YFLogxK

U2 - 10.1109/APCCAS.2018.8605570

DO - 10.1109/APCCAS.2018.8605570

M3 - Conference contribution

AN - SCOPUS:85062208056

T3 - 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018

SP - 291

EP - 294

BT - 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018

PB - Institute of Electrical and Electronics Engineers Inc.

ER -