Low-cost IP core test using multiple-mode loading scan chain and scan chain clusters

Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A fixing-shifting encoding (FSE) method is proposed to reduce test cost of IP cores. The FSE method reduces test cost by supporting multiple-mode loading test data, i.e., parallel loading, left-direction, and right-direction serial loading for each test slice data. Furthermore, the FSE that utilizes only two test channels can support a large number of internal scan chains and achieve further reduction in test cost by combining with scan chain clustering method. As a non-intrusive and automatic test pattern generation (ATPG) independent solution, the approach is applicable to IP core testing because it requires neither redesign of the core under test (CUT) nor running any additional ATPG for the encoding procedure. In addition, the decoder has low hardware overhead, and its design is independent of the CUT. Experimental results for some large ISCAS 89 benchmarks and an industry ASIC design have proven the efficiency of the proposed approach.

Original languageEnglish
Title of host publicationProceedings - 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT'06
Pages136-144
Number of pages9
DOIs
Publication statusPublished - 2006 Dec 1
Event2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Arlington, VA, United States
Duration: 2006 Oct 42006 Oct 6

Publication series

NameProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN (Print)1550-5774

Conference

Conference2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
CountryUnited States
CityArlington, VA
Period06/10/406/10/6

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Zeng, G., Shi, Y., Takabatake, T., Yanagisawa, M., & Ito, H. (2006). Low-cost IP core test using multiple-mode loading scan chain and scan chain clusters. In Proceedings - 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT'06 (pp. 136-144). [4030924] (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). https://doi.org/10.1109/DFT.2006.41