Low-cost IP core test using multiple-mode loading scan chain and scan chain clusters

Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    A fixing-shifting encoding (FSE) method is proposed to reduce test cost of IP cores. The FSE method reduces test cost by supporting multiple-mode loading test data, i.e., parallel loading, left-direction, and right-direction serial loading for each test slice data. Furthermore, the FSE that utilizes only two test channels can support a large number of internal scan chains and achieve further reduction in test cost by combining with scan chain clustering method. As a non-intrusive and automatic test pattern generation (ATPG) independent solution, the approach is applicable to IP core testing because it requires neither redesign of the core under test (CUT) nor running any additional ATPG for the encoding procedure. In addition, the decoder has low hardware overhead, and its design is independent of the CUT. Experimental results for some large ISCAS 89 benchmarks and an industry ASIC design have proven the efficiency of the proposed approach.

    Original languageEnglish
    Title of host publicationProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
    Pages136-144
    Number of pages9
    DOIs
    Publication statusPublished - 2006
    Event2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Arlington, VA
    Duration: 2006 Oct 42006 Oct 6

    Other

    Other2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
    CityArlington, VA
    Period06/10/406/10/6

    Fingerprint

    Automatic test pattern generation
    Costs
    Application specific integrated circuits
    Hardware
    Testing
    Intellectual property core
    Industry

    ASJC Scopus subject areas

    • Engineering(all)

    Cite this

    Zeng, G., Shi, Y., Takabatake, T., Yanagisawa, M., & Ito, H. (2006). Low-cost IP core test using multiple-mode loading scan chain and scan chain clusters. In Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (pp. 136-144). [4030924] https://doi.org/10.1109/DFT.2006.41

    Low-cost IP core test using multiple-mode loading scan chain and scan chain clusters. / Zeng, Gang; Shi, Youhua; Takabatake, Toshinori; Yanagisawa, Masao; Ito, Hideo.

    Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2006. p. 136-144 4030924.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Zeng, G, Shi, Y, Takabatake, T, Yanagisawa, M & Ito, H 2006, Low-cost IP core test using multiple-mode loading scan chain and scan chain clusters. in Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems., 4030924, pp. 136-144, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Arlington, VA, 06/10/4. https://doi.org/10.1109/DFT.2006.41
    Zeng G, Shi Y, Takabatake T, Yanagisawa M, Ito H. Low-cost IP core test using multiple-mode loading scan chain and scan chain clusters. In Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2006. p. 136-144. 4030924 https://doi.org/10.1109/DFT.2006.41
    Zeng, Gang ; Shi, Youhua ; Takabatake, Toshinori ; Yanagisawa, Masao ; Ito, Hideo. / Low-cost IP core test using multiple-mode loading scan chain and scan chain clusters. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2006. pp. 136-144
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