Low-power motion estimation processor with 3D stacked memory

Shuping Zhang, Jinjia Zhou, Dajiang Zhou, Shinji Kimura, Satoshi Goto

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Motion estimation (ME) is a key encoding component of almost all modern video coding standards. ME contributes significantly to video coding efficiency, but, it also consumes the most power of any component in a video encoder. In this paper, an ME processor with 3D stacked memory architecture is proposed to reduce memory and core power consumption. First, a memory die is designed and stacked with ME die. By adding face-to-face (F2F) pads and through-silicon-via (TSV) definitions, 2D electronic design automation (EDA) tools can be extended to support the proposed 3D stacking architecture. Moreover, a special memory controller is applied to control data transmission and timing between the memory die and the ME processor die. Finally, a 3D physical design is completed for the entire system. This design includes TSV/F2F placement, floor plan optimization, and power network generation. Compared to 2D technology, the number of input/output (IO) pins is reduced by 77%. After optimizing the floor plan of the processor die and memory die, the routing wire lengths are reduced by 13.4% and 50%, respectively. The stacking static random access memory contributes the most power reduction in this work. The simulation results show that the design can support real-time 720p @ 60 fps encoding at 8MHz using less than 65mW in power, which is much better compared to the state-of-the-art ME processor

Original languageEnglish
Pages (from-to)1431-1441
Number of pages11
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE98A
Issue number7
DOIs
Publication statusPublished - 2015 Jul 1

Fingerprint

Motion Estimation
Motion estimation
Die
Data storage equipment
Image coding
Video Coding
Stacking
Silicon
Encoding
Memory architecture
Design Automation
Random Access
Data communication systems
Encoder
Data Transmission
Electric power utilization
Placement
Power Consumption
Timing
Wire

Keywords

  • 3dic design
  • Low power design
  • Memory stacking
  • Motion estimation processor

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Graphics and Computer-Aided Design
  • Applied Mathematics
  • Signal Processing

Cite this

Low-power motion estimation processor with 3D stacked memory. / Zhang, Shuping; Zhou, Jinjia; Zhou, Dajiang; Kimura, Shinji; Goto, Satoshi.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E98A, No. 7, 01.07.2015, p. 1431-1441.

Research output: Contribution to journalArticle

Zhang, Shuping ; Zhou, Jinjia ; Zhou, Dajiang ; Kimura, Shinji ; Goto, Satoshi. / Low-power motion estimation processor with 3D stacked memory. In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2015 ; Vol. E98A, No. 7. pp. 1431-1441.
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