Low-power on-chip charge-recycling dc-dc conversion circuit and system

Kazuhiro Ueda, Fukashi Morishita, Shunsuke Okura, Leona Okamura, Tsutomu Yoshihara, Kazutami Arimoto

    Research output: Contribution to journalArticle

    7 Citations (Scopus)

    Abstract

    A charge-recycling circuit and system that reuses the energy between two or more stacked CPUs is proposed in order to double the life of a battery. In this architecture, CPUs are divided into upper and lower load groups, and electrical charges are shared among the stacked CPUs and a tank capacitor. Charges are temporarily stored in the tank capacitor and are then reused. To control divided loads, a high-speed and energy-efficient regulator is needed. Internal circuit voltage variation between the upper and lower modules is determined by seven low-drop-out (LDO) regulators, a voltage-boosting capacitor circuit, and the tank capacitor. As a result, stable voltage can be supplied to each CPU, even if the upper and lower loads are different or a battery is being used. The LDOs improve the margin of collection in the tank capacitor or task schedule operation, and power efficiency is raised even further. The circuit can be implemented on silicon without a large external control circuit and inductor such as a switching regulator. This circuit was applied to an in-vehicle lock-step system because the upper and lower loads and tasks are the same. Additionally, by using the proposed task scheduling to maximize efficiency, this circuit can be applied not only to lock-step systems but also to general systems. Test chips were fabricated using 90-nm standard CMOS technology. Although the maximum power efficiency of a conventional circuit with a simple LDO is 44.4%, efficiency of the proposed charge-recycling circuit turned out to be as high as 87.1% with the test chips.

    Original languageEnglish
    Article number6578586
    Pages (from-to)2608-2617
    Number of pages10
    JournalIEEE Journal of Solid-State Circuits
    Volume48
    Issue number11
    DOIs
    Publication statusPublished - 2013

    Fingerprint

    Recycling
    Networks (circuits)
    Capacitors
    Program processors
    Electric potential
    Scheduling
    Silicon

    Keywords

    • Charge-recycling
    • CPU
    • Dc-dc conversion
    • In-vehicle LSI
    • Lock-step system
    • Low drop out (LDO)
    • Task scheduling

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Ueda, K., Morishita, F., Okura, S., Okamura, L., Yoshihara, T., & Arimoto, K. (2013). Low-power on-chip charge-recycling dc-dc conversion circuit and system. IEEE Journal of Solid-State Circuits, 48(11), 2608-2617. [6578586]. https://doi.org/10.1109/JSSC.2013.2274829

    Low-power on-chip charge-recycling dc-dc conversion circuit and system. / Ueda, Kazuhiro; Morishita, Fukashi; Okura, Shunsuke; Okamura, Leona; Yoshihara, Tsutomu; Arimoto, Kazutami.

    In: IEEE Journal of Solid-State Circuits, Vol. 48, No. 11, 6578586, 2013, p. 2608-2617.

    Research output: Contribution to journalArticle

    Ueda, K, Morishita, F, Okura, S, Okamura, L, Yoshihara, T & Arimoto, K 2013, 'Low-power on-chip charge-recycling dc-dc conversion circuit and system', IEEE Journal of Solid-State Circuits, vol. 48, no. 11, 6578586, pp. 2608-2617. https://doi.org/10.1109/JSSC.2013.2274829
    Ueda K, Morishita F, Okura S, Okamura L, Yoshihara T, Arimoto K. Low-power on-chip charge-recycling dc-dc conversion circuit and system. IEEE Journal of Solid-State Circuits. 2013;48(11):2608-2617. 6578586. https://doi.org/10.1109/JSSC.2013.2274829
    Ueda, Kazuhiro ; Morishita, Fukashi ; Okura, Shunsuke ; Okamura, Leona ; Yoshihara, Tsutomu ; Arimoto, Kazutami. / Low-power on-chip charge-recycling dc-dc conversion circuit and system. In: IEEE Journal of Solid-State Circuits. 2013 ; Vol. 48, No. 11. pp. 2608-2617.
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