Low power placement and routing for the coarse-grained power gating FPGA architecture

Ce Li, Yiping Dong, Takahiro Watanabe

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Since the power consumption of FPGA is larger than that of ASIC under the condition to perform the same function using the same scaling, the application of FPGA is limited especially in portable electronic devices. In this paper, we propose a novel low-power FPGA architecture based on coarse-grained power gating to reduce power consumption. The new placement algorithm and routing resource graph for sleep regions is also presented. After enhancing the CAD framework, a detailed discussion is given under different region size supported by the new FPGA architecture. As a result, our proposed FPGA architecture combined with the new placement and routing algorithm can reduce 19.4% in the total power consumption compared with the traditional FPGA. By using our proposed method, FPGA is promising to be widely applied to portable devices.

Original languageEnglish
Pages (from-to)2519-2527
Number of pages9
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE94-A
Issue number12
DOIs
Publication statusPublished - 2011 Dec

Fingerprint

Field Programmable Gate Array
Placement
Field programmable gate arrays (FPGA)
Routing
Power Consumption
Electric power utilization
Sleep
Application specific integrated circuits
Routing algorithms
Routing Algorithm
Architecture
Computer aided design
Electronics
Scaling
Resources
Graph in graph theory

Keywords

  • FPGA
  • Low power
  • Power consumption
  • Power domain

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Graphics and Computer-Aided Design
  • Applied Mathematics
  • Signal Processing

Cite this

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