Low power test compression technique for designs with multiple scan chains

Youhua Shi*, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)


This paper presents a new DFT technique that can significantly reduce test data volume as well as scan-in power consumption for multiscan-based designs. It can also help to reduce test time and tester channel requirements with small hardware overhead. In the proposed approach, we start with apre-computed test cube set and fill the don't-cares with proper values for joint reduction of test data volume and scan power consumption. In addition we explore the linear dependencies of the scan chains to construct a fanout structure only with inverters to achieve further compression. Experimental results for the larger ISCAS'89 benchmarks show the efficiency of the proposed technique.

Original languageEnglish
Title of host publicationProceedings - 14th Asian Test Symposium, ATS 2005
Number of pages4
Publication statusPublished - 2005
Event14th Asian Test Symposium, ATS 2005 - Calcutta, India
Duration: 2005 Dec 182005 Dec 21

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735


Conference14th Asian Test Symposium, ATS 2005

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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