Low power test compression technique for designs with multiple scan chains

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)

Abstract

This paper presents a new DFT technique that can significantly reduce test data volume as well as scan-in power consumption for multiscan-based designs. It can also help to reduce test time and tester channel requirements with small hardware overhead. In the proposed approach, we start with apre-computed test cube set and fill the don't-cares with proper values for joint reduction of test data volume and scan power consumption. In addition we explore the linear dependencies of the scan chains to construct a fanout structure only with inverters to achieve further compression. Experimental results for the larger ISCAS'89 benchmarks show the efficiency of the proposed technique.

Original languageEnglish
Title of host publicationProceedings of the Asian Test Symposium
Pages386-389
Number of pages4
Volume2005
DOIs
Publication statusPublished - 2005
Event14th Asian Test Symposium, ATS 2005 - Calcutta
Duration: 2005 Dec 182005 Dec 21

Other

Other14th Asian Test Symposium, ATS 2005
CityCalcutta
Period05/12/1805/12/21

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Electric power utilization
Discrete Fourier transforms
Hardware

ASJC Scopus subject areas

  • Media Technology
  • Hardware and Architecture

Cite this

Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M., & Ohtsuki, T. (2005). Low power test compression technique for designs with multiple scan chains. In Proceedings of the Asian Test Symposium (Vol. 2005, pp. 386-389). [1575460] https://doi.org/10.1109/ATS.2005.76

Low power test compression technique for designs with multiple scan chains. / Shi, Youhua; Togawa, Nozomu; Kimura, Shinji; Yanagisawa, Masao; Ohtsuki, Tatsuo.

Proceedings of the Asian Test Symposium. Vol. 2005 2005. p. 386-389 1575460.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Shi, Y, Togawa, N, Kimura, S, Yanagisawa, M & Ohtsuki, T 2005, Low power test compression technique for designs with multiple scan chains. in Proceedings of the Asian Test Symposium. vol. 2005, 1575460, pp. 386-389, 14th Asian Test Symposium, ATS 2005, Calcutta, 05/12/18. https://doi.org/10.1109/ATS.2005.76
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