Low power test compression technique for designs with multiple scan chains

Youhua Shi; Nozomu Togawa; Shinji Kimura; Masao Yanagisawa; Tatsuo Ohtsuki

doi:10.1109/ATS.2005.76

Low power test compression technique for designs with multiple scan chains

Youhua Shi^*, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

17 Citations (Scopus)

Abstract

This paper presents a new DFT technique that can significantly reduce test data volume as well as scan-in power consumption for multiscan-based designs. It can also help to reduce test time and tester channel requirements with small hardware overhead. In the proposed approach, we start with apre-computed test cube set and fill the don't-cares with proper values for joint reduction of test data volume and scan power consumption. In addition we explore the linear dependencies of the scan chains to construct a fanout structure only with inverters to achieve further compression. Experimental results for the larger ISCAS'89 benchmarks show the efficiency of the proposed technique.

Original language	English
Title of host publication	Proceedings - 14th Asian Test Symposium, ATS 2005
Pages	386-389
Number of pages	4
DOIs	https://doi.org/10.1109/ATS.2005.76
Publication status	Published - 2005
Event	14th Asian Test Symposium, ATS 2005 - Calcutta, India Duration: 2005 Dec 18 → 2005 Dec 21

Publication series

Name	Proceedings of the Asian Test Symposium
Volume	2005
ISSN (Print)	1081-7735

Conference

Conference	14th Asian Test Symposium, ATS 2005
Country/Territory	India
City	Calcutta
Period	05/12/18 → 05/12/21

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/ATS.2005.76

Cite this

@inproceedings{b2becc8cc2414a2e9e041e0ecc88201e,

title = "Low power test compression technique for designs with multiple scan chains",

abstract = "This paper presents a new DFT technique that can significantly reduce test data volume as well as scan-in power consumption for multiscan-based designs. It can also help to reduce test time and tester channel requirements with small hardware overhead. In the proposed approach, we start with apre-computed test cube set and fill the don't-cares with proper values for joint reduction of test data volume and scan power consumption. In addition we explore the linear dependencies of the scan chains to construct a fanout structure only with inverters to achieve further compression. Experimental results for the larger ISCAS'89 benchmarks show the efficiency of the proposed technique.",

author = "Youhua Shi and Nozomu Togawa and Shinji Kimura and Masao Yanagisawa and Tatsuo Ohtsuki",

year = "2005",

doi = "10.1109/ATS.2005.76",

language = "English",

isbn = "0769524818",

series = "Proceedings of the Asian Test Symposium",

pages = "386--389",

booktitle = "Proceedings - 14th Asian Test Symposium, ATS 2005",

note = "14th Asian Test Symposium, ATS 2005 ; Conference date: 18-12-2005 Through 21-12-2005",

}

TY - GEN

T1 - Low power test compression technique for designs with multiple scan chains

AU - Shi, Youhua

AU - Togawa, Nozomu

AU - Kimura, Shinji

AU - Yanagisawa, Masao

AU - Ohtsuki, Tatsuo

PY - 2005

Y1 - 2005

N2 - This paper presents a new DFT technique that can significantly reduce test data volume as well as scan-in power consumption for multiscan-based designs. It can also help to reduce test time and tester channel requirements with small hardware overhead. In the proposed approach, we start with apre-computed test cube set and fill the don't-cares with proper values for joint reduction of test data volume and scan power consumption. In addition we explore the linear dependencies of the scan chains to construct a fanout structure only with inverters to achieve further compression. Experimental results for the larger ISCAS'89 benchmarks show the efficiency of the proposed technique.

AB - This paper presents a new DFT technique that can significantly reduce test data volume as well as scan-in power consumption for multiscan-based designs. It can also help to reduce test time and tester channel requirements with small hardware overhead. In the proposed approach, we start with apre-computed test cube set and fill the don't-cares with proper values for joint reduction of test data volume and scan power consumption. In addition we explore the linear dependencies of the scan chains to construct a fanout structure only with inverters to achieve further compression. Experimental results for the larger ISCAS'89 benchmarks show the efficiency of the proposed technique.

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U2 - 10.1109/ATS.2005.76

DO - 10.1109/ATS.2005.76

M3 - Conference contribution

AN - SCOPUS:33846924119

SN - 0769524818

SN - 9780769524818

T3 - Proceedings of the Asian Test Symposium

SP - 386

EP - 389

BT - Proceedings - 14th Asian Test Symposium, ATS 2005

T2 - 14th Asian Test Symposium, ATS 2005

Y2 - 18 December 2005 through 21 December 2005

ER -

Low power test compression technique for designs with multiple scan chains

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