Low voltage operation of sub-quarter micron W-polycide dual gate CMOS with non-uniformly doped channel

H. Sayama, T. Kuroi, S. Shimizu, M. Shirahata, Y. Okumura, Masahide Inuishi, H. Miyoshi

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

A 0.25 μm W-polycide dual gate CMOS has been newly developed for a logic in DRAM under low voltage operation. A novel gate electrode can eliminate inter-diffusion and the gate depletion using a barrier oxide film against dopant diffusion, so that a dual gate CMOS can be fabricated with sufficient thermal budget. Moreover, low threshold voltage and high current drivability can be obtained by non-uniformly doped channel structure formed by the oblique rotational ion implantation utilizing W-polycide gate as a mask. As a result, a high performance has been achieved.

Original languageEnglish
Pages (from-to)583-586
Number of pages4
JournalUnknown Journal
Publication statusPublished - 1996
Externally publishedYes

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Sayama, H., Kuroi, T., Shimizu, S., Shirahata, M., Okumura, Y., Inuishi, M., & Miyoshi, H. (1996). Low voltage operation of sub-quarter micron W-polycide dual gate CMOS with non-uniformly doped channel. Unknown Journal, 583-586.