Low voltage operation of sub-quarter micron W-polycide dual gate CMOS with non-uniformly doped channel

H. Sayama; T. Kuroi; S. Shimizu; M. Shirahata; Y. Okumura; M. Inuishi; H. Miyoshi

Low voltage operation of sub-quarter micron W-polycide dual gate CMOS with non-uniformly doped channel

H. Sayama^*, T. Kuroi, S. Shimizu, M. Shirahata, Y. Okumura, M. Inuishi, H. Miyoshi

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

4 Citations (Scopus)

Abstract

A 0.25 μm W-polycide dual gate CMOS has been newly developed for a logic in DRAM under low voltage operation. A novel gate electrode can eliminate inter-diffusion and the gate depletion using a barrier oxide film against dopant diffusion, so that a dual gate CMOS can be fabricated with sufficient thermal budget. Moreover, low threshold voltage and high current drivability can be obtained by non-uniformly doped channel structure formed by the oblique rotational ion implantation utilizing W-polycide gate as a mask. As a result, a high performance has been achieved.

Original language	English
Pages (from-to)	583-586
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
Publication status	Published - 1996 Dec 1
Externally published	Yes
Event	Proceedings of the 1996 IEEE International Electron Devices Meeting - San Francisco, CA, USA Duration: 1996 Dec 8 → 1996 Dec 11

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Cite this

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title = "Low voltage operation of sub-quarter micron W-polycide dual gate CMOS with non-uniformly doped channel",

abstract = "A 0.25 μm W-polycide dual gate CMOS has been newly developed for a logic in DRAM under low voltage operation. A novel gate electrode can eliminate inter-diffusion and the gate depletion using a barrier oxide film against dopant diffusion, so that a dual gate CMOS can be fabricated with sufficient thermal budget. Moreover, low threshold voltage and high current drivability can be obtained by non-uniformly doped channel structure formed by the oblique rotational ion implantation utilizing W-polycide gate as a mask. As a result, a high performance has been achieved.",

author = "H. Sayama and T. Kuroi and S. Shimizu and M. Shirahata and Y. Okumura and M. Inuishi and H. Miyoshi",

year = "1996",

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journal = "Technical Digest - International Electron Devices Meeting",

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note = "Proceedings of the 1996 IEEE International Electron Devices Meeting ; Conference date: 08-12-1996 Through 11-12-1996",

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T1 - Low voltage operation of sub-quarter micron W-polycide dual gate CMOS with non-uniformly doped channel

AU - Sayama, H.

AU - Kuroi, T.

AU - Shimizu, S.

AU - Shirahata, M.

AU - Okumura, Y.

AU - Inuishi, M.

AU - Miyoshi, H.

PY - 1996/12/1

Y1 - 1996/12/1

N2 - A 0.25 μm W-polycide dual gate CMOS has been newly developed for a logic in DRAM under low voltage operation. A novel gate electrode can eliminate inter-diffusion and the gate depletion using a barrier oxide film against dopant diffusion, so that a dual gate CMOS can be fabricated with sufficient thermal budget. Moreover, low threshold voltage and high current drivability can be obtained by non-uniformly doped channel structure formed by the oblique rotational ion implantation utilizing W-polycide gate as a mask. As a result, a high performance has been achieved.

AB - A 0.25 μm W-polycide dual gate CMOS has been newly developed for a logic in DRAM under low voltage operation. A novel gate electrode can eliminate inter-diffusion and the gate depletion using a barrier oxide film against dopant diffusion, so that a dual gate CMOS can be fabricated with sufficient thermal budget. Moreover, low threshold voltage and high current drivability can be obtained by non-uniformly doped channel structure formed by the oblique rotational ion implantation utilizing W-polycide gate as a mask. As a result, a high performance has been achieved.

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M3 - Conference article

AN - SCOPUS:0030398598

SP - 583

EP - 586

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

SN - 0163-1918

T2 - Proceedings of the 1996 IEEE International Electron Devices Meeting

Y2 - 8 December 1996 through 11 December 1996

ER -

Low voltage operation of sub-quarter micron W-polycide dual gate CMOS with non-uniformly doped channel

Abstract

ASJC Scopus subject areas

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