Low voltage operation of sub-quarter micron W-polycide dual gate CMOS with non-uniformly doped channel

H. Sayama, T. Kuroi, S. Shimizu, M. Shirahata, Y. Okumura, Masahide Inuishi, H. Miyoshi

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

A 0.25 μm W-polycide dual gate CMOS has been newly developed for a logic in DRAM under low voltage operation. A novel gate electrode can eliminate inter-diffusion and the gate depletion using a barrier oxide film against dopant diffusion, so that a dual gate CMOS can be fabricated with sufficient thermal budget. Moreover, low threshold voltage and high current drivability can be obtained by non-uniformly doped channel structure formed by the oblique rotational ion implantation utilizing W-polycide gate as a mask. As a result, a high performance has been achieved.

Original languageEnglish
Pages (from-to)583-586
Number of pages4
JournalUnknown Journal
Publication statusPublished - 1996
Externally publishedYes

Fingerprint

Dynamic random access storage
Threshold voltage
Ion implantation
low voltage
Oxide films
Masks
CMOS
Doping (additives)
Electrodes
Electric potential
budgets
threshold voltage
logic
high current
oxide films
ion implantation
depletion
masks
Hot Temperature
electrodes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Sayama, H., Kuroi, T., Shimizu, S., Shirahata, M., Okumura, Y., Inuishi, M., & Miyoshi, H. (1996). Low voltage operation of sub-quarter micron W-polycide dual gate CMOS with non-uniformly doped channel. Unknown Journal, 583-586.

Low voltage operation of sub-quarter micron W-polycide dual gate CMOS with non-uniformly doped channel. / Sayama, H.; Kuroi, T.; Shimizu, S.; Shirahata, M.; Okumura, Y.; Inuishi, Masahide; Miyoshi, H.

In: Unknown Journal, 1996, p. 583-586.

Research output: Contribution to journalArticle

Sayama, H, Kuroi, T, Shimizu, S, Shirahata, M, Okumura, Y, Inuishi, M & Miyoshi, H 1996, 'Low voltage operation of sub-quarter micron W-polycide dual gate CMOS with non-uniformly doped channel', Unknown Journal, pp. 583-586.
Sayama, H. ; Kuroi, T. ; Shimizu, S. ; Shirahata, M. ; Okumura, Y. ; Inuishi, Masahide ; Miyoshi, H. / Low voltage operation of sub-quarter micron W-polycide dual gate CMOS with non-uniformly doped channel. In: Unknown Journal. 1996 ; pp. 583-586.
@article{47dce0884ee0420181b329cdbb22f214,
title = "Low voltage operation of sub-quarter micron W-polycide dual gate CMOS with non-uniformly doped channel",
abstract = "A 0.25 μm W-polycide dual gate CMOS has been newly developed for a logic in DRAM under low voltage operation. A novel gate electrode can eliminate inter-diffusion and the gate depletion using a barrier oxide film against dopant diffusion, so that a dual gate CMOS can be fabricated with sufficient thermal budget. Moreover, low threshold voltage and high current drivability can be obtained by non-uniformly doped channel structure formed by the oblique rotational ion implantation utilizing W-polycide gate as a mask. As a result, a high performance has been achieved.",
author = "H. Sayama and T. Kuroi and S. Shimizu and M. Shirahata and Y. Okumura and Masahide Inuishi and H. Miyoshi",
year = "1996",
language = "English",
pages = "583--586",
journal = "Nuclear Physics A",
issn = "0375-9474",
publisher = "Elsevier",

}

TY - JOUR

T1 - Low voltage operation of sub-quarter micron W-polycide dual gate CMOS with non-uniformly doped channel

AU - Sayama, H.

AU - Kuroi, T.

AU - Shimizu, S.

AU - Shirahata, M.

AU - Okumura, Y.

AU - Inuishi, Masahide

AU - Miyoshi, H.

PY - 1996

Y1 - 1996

N2 - A 0.25 μm W-polycide dual gate CMOS has been newly developed for a logic in DRAM under low voltage operation. A novel gate electrode can eliminate inter-diffusion and the gate depletion using a barrier oxide film against dopant diffusion, so that a dual gate CMOS can be fabricated with sufficient thermal budget. Moreover, low threshold voltage and high current drivability can be obtained by non-uniformly doped channel structure formed by the oblique rotational ion implantation utilizing W-polycide gate as a mask. As a result, a high performance has been achieved.

AB - A 0.25 μm W-polycide dual gate CMOS has been newly developed for a logic in DRAM under low voltage operation. A novel gate electrode can eliminate inter-diffusion and the gate depletion using a barrier oxide film against dopant diffusion, so that a dual gate CMOS can be fabricated with sufficient thermal budget. Moreover, low threshold voltage and high current drivability can be obtained by non-uniformly doped channel structure formed by the oblique rotational ion implantation utilizing W-polycide gate as a mask. As a result, a high performance has been achieved.

UR - http://www.scopus.com/inward/record.url?scp=0030398598&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030398598&partnerID=8YFLogxK

M3 - Article

SP - 583

EP - 586

JO - Nuclear Physics A

JF - Nuclear Physics A

SN - 0375-9474

ER -