Abstract
A 0.25 μm W-polycide dual gate CMOS has been newly developed for a logic in DRAM under low voltage operation. A novel gate electrode can eliminate inter-diffusion and the gate depletion using a barrier oxide film against dopant diffusion, so that a dual gate CMOS can be fabricated with sufficient thermal budget. Moreover, low threshold voltage and high current drivability can be obtained by non-uniformly doped channel structure formed by the oblique rotational ion implantation utilizing W-polycide gate as a mask. As a result, a high performance has been achieved.
| Original language | English |
|---|---|
| Pages (from-to) | 583-586 |
| Number of pages | 4 |
| Journal | Technical Digest - International Electron Devices Meeting |
| Publication status | Published - 1996 Dec 1 |
| Event | Proceedings of the 1996 IEEE International Electron Devices Meeting - San Francisco, CA, USA Duration: 1996 Dec 8 → 1996 Dec 11 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Materials Chemistry
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Cite this
Sayama, H., Kuroi, T., Shimizu, S., Shirahata, M., Okumura, Y., Inuishi, M., & Miyoshi, H. (1996). Low voltage operation of sub-quarter micron W-polycide dual gate CMOS with non-uniformly doped channel. Technical Digest - International Electron Devices Meeting, 583-586.