Low voltage operation of sub-quarter micron W-polycide dual gate CMOS with non-uniformly doped channel

H. Sayama, T. Kuroi, S. Shimizu, M. Shirahata, Y. Okumura, M. Inuishi, H. Miyoshi

Research output: Contribution to journalConference article

3 Citations (Scopus)

Abstract

A 0.25 μm W-polycide dual gate CMOS has been newly developed for a logic in DRAM under low voltage operation. A novel gate electrode can eliminate inter-diffusion and the gate depletion using a barrier oxide film against dopant diffusion, so that a dual gate CMOS can be fabricated with sufficient thermal budget. Moreover, low threshold voltage and high current drivability can be obtained by non-uniformly doped channel structure formed by the oblique rotational ion implantation utilizing W-polycide gate as a mask. As a result, a high performance has been achieved.

Original languageEnglish
Pages (from-to)583-586
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 1996 Dec 1
Externally publishedYes
EventProceedings of the 1996 IEEE International Electron Devices Meeting - San Francisco, CA, USA
Duration: 1996 Dec 81996 Dec 11

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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