Maple: a simultaneous technology mapping, placement, and global routing algorithm for FPGAs

Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki

Research output: Contribution to conferencePaper

Abstract

Technology mapping algorithms for LUT (Look Up Table) based FPGAs have been proposed to transfer a Boolean network into logic-blocks. However, since those algorithms take no layout information into account, they do not always lead to excellent results. In this paper, a simultaneous technology mapping, placement and global routing algorithm for FPGAs, Maple, is presented. Maple is an extended version of a simultaneous placement and global routing algorithm for FPGAs, which is based on recursive partition of layout regions and block sets. Maple inherits its basic process and executes the technology mapping simultaneously in each recursive process. Therefore, the mapping can be done with the placement and global routing information. Experimental results for some benchmark circuits demonstrate its efficiency and effectiveness.

Original languageEnglish
Pages554-559
Number of pages6
Publication statusPublished - 1994 Dec 1
EventProceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems - Taipei, Taiwan
Duration: 1994 Dec 51994 Dec 8

Other

OtherProceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems
CityTaipei, Taiwan
Period94/12/594/12/8

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Togawa, N., Sato, M., & Ohtsuki, T. (1994). Maple: a simultaneous technology mapping, placement, and global routing algorithm for FPGAs. 554-559. Paper presented at Proceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems, Taipei, Taiwan, .