Maple

a simultaneous technology mapping, placement, and global routing algorithm for FPGAs

Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    Technology mapping algorithms for LUT (Look Up Table) based FPGAs have been proposed to transfer a Boolean network into logic-blocks. However, since those algorithms take no layout information into account, they do not always lead to excellent results. In this paper, a simultaneous technology mapping, placement and global routing algorithm for FPGAs, Maple, is presented. Maple is an extended version of a simultaneous placement and global routing algorithm for FPGAs, which is based on recursive partition of layout regions and block sets. Maple inherits its basic process and executes the technology mapping simultaneously in each recursive process. Therefore, the mapping can be done with the placement and global routing information. Experimental results for some benchmark circuits demonstrate its efficiency and effectiveness.

    Original languageEnglish
    Title of host publicationIEEE Asia-Pacific Conference on Circuits and Systems - Proceedings
    Place of PublicationPiscataway, NJ, United States
    PublisherIEEE
    Pages554-559
    Number of pages6
    Publication statusPublished - 1994
    EventProceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems - Taipei, Taiwan
    Duration: 1994 Dec 51994 Dec 8

    Other

    OtherProceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems
    CityTaipei, Taiwan
    Period94/12/594/12/8

    Fingerprint

    Routing algorithms
    Field programmable gate arrays (FPGA)
    Networks (circuits)

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Togawa, N., Sato, M., & Ohtsuki, T. (1994). Maple: a simultaneous technology mapping, placement, and global routing algorithm for FPGAs. In IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings (pp. 554-559). Piscataway, NJ, United States: IEEE.

    Maple : a simultaneous technology mapping, placement, and global routing algorithm for FPGAs. / Togawa, Nozomu; Sato, Masao; Ohtsuki, Tatsuo.

    IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. Piscataway, NJ, United States : IEEE, 1994. p. 554-559.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Togawa, N, Sato, M & Ohtsuki, T 1994, Maple: a simultaneous technology mapping, placement, and global routing algorithm for FPGAs. in IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. IEEE, Piscataway, NJ, United States, pp. 554-559, Proceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems, Taipei, Taiwan, 94/12/5.
    Togawa N, Sato M, Ohtsuki T. Maple: a simultaneous technology mapping, placement, and global routing algorithm for FPGAs. In IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. Piscataway, NJ, United States: IEEE. 1994. p. 554-559
    Togawa, Nozomu ; Sato, Masao ; Ohtsuki, Tatsuo. / Maple : a simultaneous technology mapping, placement, and global routing algorithm for FPGAs. IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. Piscataway, NJ, United States : IEEE, 1994. pp. 554-559
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